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[71.236.167.8]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a0df64b233sm422959a91.2.2026.09.25.19.00.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 19:00:41 -0700 (PDT) From: Nikolas Joshua Britton To: Ilpo =?utf-8?q?J=C3=A4rvinen?= Cc: Maciej Grochowski , Geramy Loveless , Eric Auger , Alexey Fomenko , Bjorn Helgaas , Lorenzo Pieralisi , Rob Herring , Krzysztof =?utf-8?q?Wilczy=C5=84ski?= , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/5] PCI: Resource placement algorithm fixes Date: Sat, 26 Sep 2026 02:00:40 +0000 Message-ID: <20260926020040.8750-1-nbritton@exabit.io> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260923131757.7792-1-ilpo.jarvinen@linux.intel.com> References: <20260923131757.7792-1-ilpo.jarvinen@linux.intel.com> Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Wed, 23 Sep 2026, Ilpo Järvinen wrote: > In addition, the series corrects composite resource sizing to account > for gaps that have to be added due to alignment constaints and > remainder space not fully connecting (filling space all the way to > the bridge window align). Hi Ilpo, Thanks, the series fixes the Mac Pro 7,1 case from my report. That is two Radeon Pro Vega II Duo cards, each with two GPU dies behind one root port, and BAR0 resized to 32 GB by setting the ReBAR control and rescanning the root port's bus (booted with pci=realloc). I tested all five patches on top of v7.2.8, where they apply without fuzz, against plain v7.2.8 built with the same config. With plain v7.2.8 it fails as in the report: the root port window is 64G+4M, and the second die gets no BAR: pci 0000:06:00.0: bridge window [mem 0x90000000000-0x910003fffff 64bit pref]: assigned pci 0000:0b:00.0: BAR 0 [mem 0x90000000000-0x907ffffffff 64bit pref]: assigned pci 0000:0e:00.0: BAR 0 [mem size 0x800000000 64bit pref]: can't assign; no space With the series, all four dies get their 32 GB BAR0, amdgpu binds all four, and they form one XGMI hive. Each root port window is now 96G (my one-liner gave 128G). The second sub-bridge window starts with the die's 2M BAR2 at its left edge, and the two nested bridges below it (0c:00.0, 0d:00.0) carry the same range: pci 0000:06:00.0: bridge window [mem 0x9e800000000-0x9ffffffffff 64bit pref]: assigned pci 0000:08:08.0: bridge window [mem 0x9e800000000-0x9f0001fffff 64bit pref]: assigned pci 0000:08:10.0: bridge window [mem 0x9f7ffe00000-0x9ffffffffff 64bit pref]: assigned pci 0000:0b:00.0: BAR 0 [mem 0x9e800000000-0x9efffffffff 64bit pref]: assigned pci 0000:0e:00.0: BAR 2 [mem 0x9f7ffe00000-0x9f7ffffffff 64bit pref]: assigned pci 0000:0e:00.0: BAR 0 [mem 0x9f800000000-0x9ffffffffff 64bit pref]: assigned The second card (root port 16:00.0) is laid out the same way. No other device lost a resource: the only "can't assign" messages left are for the same I/O windows that fail on every kernel on this machine. I used v7.2.8 rather than your v7.3-rc1 base because v7.3-rc4 powers this machine off during boot, with or without the series. I haven't looked into that yet. Tested-by: Nikolas Joshua Britton