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Fri, 25 Sep 2026 23:12:12 -0700 (PDT) X-Received: by 2002:a05:600c:1d0d:b0:49c:f4e1:4c2d with SMTP id 5b1f17b1804b1-49fe66f144fmr139781965e9.16.1790403132386; Fri, 25 Sep 2026 23:12:12 -0700 (PDT) Received: from [192.168.10.48] ([151.49.232.249]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49fe5cd4c8dsm218640265e9.3.2026.09.25.23.12.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 25 Sep 2026 23:12:11 -0700 (PDT) From: Paolo Bonzini To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Cc: seanjc@google.com Subject: Re: [PATCH 00/11] KVM: fix issues with stale control fields Date: Sat, 26 Sep 2026 08:12:11 +0200 Message-ID: <20260926061211.714733-1-pbonzini@redhat.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20260926053253.195597-1-pbonzini@redhat.com> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable > Fix two bugs where the guest could do stupid things on purpose to=0D > cause problems in the host.=0D >=0D > Patches 1-5 cover cases where actions done through VMCB control fields=0D > have to be redone if VMRUN fails. In particular, failed VMRUNs can=0D > cause pending TLB flushes to be dropped.=0D >=0D > Patch 6 fixes a case where eVMCS execution controls can cause the=0D > host to use a stale MSR permission bitmap. Patches 7-11 are tests=0D > for nested x2APIC; don't run them on an unpatched kernel.=0D =0D In addition to what was reported by Sashiko, the test does not pass on=0D SVM. Fixed as follows:=0D =0D diff --git a/tools/testing/selftests/kvm/x86/nested_x2apic_test.c b/tools/t= esting/selftests/kvm/x86/nested_x2apic_test.c=0D index eb89d5bfc0fe..ce204ce29a9c 100644=0D --- a/tools/testing/selftests/kvm/x86/nested_x2apic_test.c=0D +++ b/tools/testing/selftests/kvm/x86/nested_x2apic_test.c=0D @@ -48,6 +48,7 @@ static void l1_svm_code(struct svm_test_data *svm)=0D GUEST_ASSERT_EQ(ctrl->exit_code, SVM_EXIT_CPUID);=0D =0D stgi();=0D + x2apic_write_reg(APIC_TASKPRI, 0);=0D }=0D =0D static void l1_vmx_code(struct vmx_pages *vmx, struct hyperv_test_pages *h= v_pages)=0D @@ -80,14 +81,12 @@ static void l1_vmx_code(struct vmx_pages *vmx, struct h= yperv_test_pages *hv_page=0D control |=3D CPU_BASED_USE_MSR_BITMAPS | CPU_BASED_TPR_SHADOW;=0D GUEST_ASSERT_EQ(vmwrite(CPU_BASED_VM_EXEC_CONTROL, control), 0);=0D =0D - if (control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {=0D - control =3D vmreadz(SECONDARY_VM_EXEC_CONTROL);=0D - control |=3D SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |=0D - SECONDARY_EXEC_APIC_REGISTER_VIRT |=0D - SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;=0D - control &=3D (rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2) >> 32);=0D - GUEST_ASSERT_EQ(vmwrite(SECONDARY_VM_EXEC_CONTROL, control), 0);=0D - }=0D + control =3D vmreadz(SECONDARY_VM_EXEC_CONTROL);=0D + control |=3D SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |=0D + SECONDARY_EXEC_APIC_REGISTER_VIRT |=0D + SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY;=0D + control &=3D (rdmsr(MSR_IA32_VMX_PROCBASED_CTLS2) >> 32);=0D + GUEST_ASSERT_EQ(vmwrite(SECONDARY_VM_EXEC_CONTROL, control), 0);=0D =0D GUEST_ASSERT(!vmlaunch());=0D GUEST_ASSERT_EQ(vmreadz(VM_EXIT_REASON), EXIT_REASON_CPUID);=0D @@ -103,7 +102,7 @@ static void l1_vmx_code_part2(void)=0D control &=3D ~CPU_BASED_TPR_SHADOW;=0D GUEST_ASSERT_EQ(vmwrite(CPU_BASED_VM_EXEC_CONTROL, control), 0);=0D =0D - control =3D vmread(SECONDARY_VM_EXEC_CONTROL, &control);=0D + control =3D vmreadz(SECONDARY_VM_EXEC_CONTROL);=0D control &=3D ~(SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |=0D SECONDARY_EXEC_APIC_REGISTER_VIRT |=0D SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);=0D @@ -154,21 +153,23 @@ static void l1_guest_code(void *test_data, void *hv_p= ages)=0D =0D l1_test_x2apic_intercepts();=0D =0D - if (this_cpu_has(X86_FEATURE_VMX))=0D + if (this_cpu_has(X86_FEATURE_VMX)) {=0D l1_vmx_code_part2();=0D -=0D - l1_test_x2apic_intercepts();=0D + l1_test_x2apic_intercepts();=0D + }=0D =0D GUEST_DONE();=0D }=0D =0D -static void __test_x2apic_intercepts(bool use_evmcs)=0D +static void test_x2apic_intercepts(bool with_inhibit_apicv, bool use_evmcs= )=0D {=0D gva_t nested_test_data_gva, hv_pages_gva =3D 0;=0D struct kvm_vcpu *vcpu;=0D struct kvm_vm *vm;=0D struct ucall uc;=0D =0D + inhibit_apicv =3D with_inhibit_apicv;=0D +=0D vm =3D vm_create_with_one_vcpu(&vcpu, l1_guest_code);=0D vm_install_exception_handler(vm, POSTED_INTR_VECTOR, guest_irq_handler);= =0D vm_install_exception_handler(vm, POSTED_INTR_WAKEUP_VECTOR, guest_irq_han= dler);=0D @@ -207,29 +208,15 @@ static void __test_x2apic_intercepts(bool use_evmcs)= =0D kvm_vm_free(vm);=0D }=0D =0D -#define _test_x2apic_intercepts(inhibit_apic_setting) \=0D -do { \=0D - \=0D - inhibit_apic_setting; \=0D - \=0D - __test_x2apic_intercepts(use_evmcs); \=0D -} while (0)=0D -=0D -#define test_x2apic_intercepts(use_evmcs_setting) \=0D -do { \=0D - bool use_evmcs_setting; \=0D - \=0D - _test_x2apic_intercepts(inhibit_apicv =3D true); \=0D - _test_x2apic_intercepts(inhibit_apicv =3D false); \=0D -} while (0)=0D -=0D -=0D int main(int argc, char *argv[])=0D {=0D TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM) || kvm_cpu_has(X86_FEATURE_VMX)= );=0D =0D - test_x2apic_intercepts(use_evmcs =3D false);=0D + test_x2apic_intercepts(true, false);=0D + test_x2apic_intercepts(false, false);=0D =0D - if (kvm_has_cap(KVM_CAP_HYPERV_ENLIGHTENED_VMCS))=0D - test_x2apic_intercepts(use_evmcs =3D true);=0D + if (kvm_has_cap(KVM_CAP_HYPERV_ENLIGHTENED_VMCS)) {=0D + test_x2apic_intercepts(true, true);=0D + test_x2apic_intercepts(false, true);=0D + }=0D }=0D =0D Paolo=0D