Re: [PATCH v2] PCI: pciehp: Avoid dropping hotplug interrupts due to\r stale HPIE

[Zhu Qiyu <qiyuzhu2@amd.com>]

Hi Lukas,

> Are you seeing this on a real-world system or is it an LLM-generated
> hallucination?

Yes, this was observed on a real system during NVMe hot-add:

  System: AMD EPYC 9554
  Port: 0000:c0:03.4, slot 71

Our PMFW temporarily clears HPIE and sets it again later, with the intent of
suppressing and then re-enabling DLSC interrupt notifications. The previously
mentioned race condition prevents the DLSC event from being processed correctly,
resulting in a failure to clear certain status flags, which in turn affects the
subsequent hot-plug state machine.

Only PDC event, no DLSC event:

[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: pciehp: pending interrupts 0x0008 from Slot Status
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: pciehp: pciehp_check_link_active: lnk_status = 5041
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: pciehp: Slot(71): Card present
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: pciehp: pciehp_set_indicators: SLOTCTRL 70 write cmd 200
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: pciehp: pciehp_check_link_status: lnk_status = f045
[Thu May 14 11:30:46 2026] pci 0000:c7:00.0: [144d:a900] type 00 class 0x010802
[Thu May 14 11:30:46 2026] pci 0000:c7:00.0: reg 0x10: [mem 0x00000000-0x00007fff 64bit]
[Thu May 14 11:30:46 2026] pci 0000:c7:00.0: Max Payload Size set to 512 (was 128, max 512)
[Thu May 14 11:30:46 2026] pci 0000:c7:00.0: Adding to iommu group 54
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: bridge window [io  0x1000-0x0fff] to [bus c7-c8] add_size 1000
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: BAR 13: no space for [io  size 0x1000]
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: BAR 13: failed to assign [io  size 0x1000]
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: BAR 13: no space for [io  size 0x1000]
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: BAR 13: failed to assign [io  size 0x1000]
[Thu May 14 11:30:46 2026] pci 0000:c7:00.0: BAR 0: assigned [mem 0xba300000-0xba307fff 64bit]
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: PCI bridge to [bus c7-c8]
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4:   bridge window [mem 0xba300000-0xba3fffff]
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4:   bridge window [mem 0x600e1600000-0x600e17fffff 64bit pref]
[Thu May 14 11:30:46 2026] nvme nvme3: pci function 0000:c7:00.0
[Thu May 14 11:30:46 2026] nvme 0000:c7:00.0: enabling device (0000 -> 0002)
[Thu May 14 11:30:46 2026] pcieport 0000:c0:03.4: pciehp: pciehp_set_indicators: SLOTCTRL 70 write cmd 1c0
[Thu May 14 11:30:48 2026] nvme nvme3: Shutdown timeout set to 8 seconds
[Thu May 14 11:30:48 2026] nvme nvme3: 256/0/0 default/read/poll queues
[Thu May 14 11:30:48 2026]  nvme3n1: p1 p2

after hot-plug, run lspci -vvv and find that the Linkstate+

DevCap:    MaxPayload 512 bytes, PhantFunc 0
ExtTag+ RBE+
DevCtl:    CorrErr+ NonFatalErr+ FatalErr+ UnsupReq-
RlxdOrd+ ExtTag+ PhantFunc- AuxPwr- NoSnoop+
MaxPayload 512 bytes, MaxReadReq 512 bytes
DevSta:    CorrErr- NonFatalErr- FatalErr- UnsupReq- AuxPwr- TransPend-
LnkCap:    Port #0, Speed 32GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
ClockPM- Surprise+ LLActRep+ BwNot+ ASPMOptComp+
LnkCtl:    ASPM Disabled; RCB 64 bytes, Disabled- CommClk+
ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
LnkSta:    Speed 32GT/s (ok), Width x4 (ok)
TrErr- Train- SlotClk+ DLActive+ BWMgmt+ ABWMgmt+
SltCap:    AttnBtn- PwrCtrl- MRL- AttnInd+ PwrInd+ HotPlug+ Surprise-
Slot #71, PowerLimit 75.000W; Interlock- NoCompl+
SltCtl:    Enable: AttnBtn- PwrFlt- MRL- PresDet+ CmdCplt- HPIrq+ LinkChg+
Control: AttnInd Off, PwrInd On, Power- Interlock-
SltSta:    Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
Changed: MRL- PresDet- LinkState+

> Firmware is not allowed to change the Slot Control Register once it has
> granted control of PCI Express Native Hot Plug Control to the operating
> system.

Thanks for pointing this out.  I checked the boot log: the host bridge
covering the affected port does grant native hotplug control to the OS.
The relevant lines, with timestamps omitted, are:

  ACPI: PCI Root Bridge [S1D1] (domain 0000 [bus c0-df])
  acpi PNP0A08:05: _OSC: platform does not support [AER LTR DPC]
  acpi PNP0A08:05: _OSC: OS now controls [PCIeHotplug SHPCHotplug PME PCIeCapability]

There is no pcie_ports=native override in the boot command line.  The
same boot also reports:

  GHES: APEI firmware first mode is enabled by APEI bit.

That refers to APEI/GHES error handling, not hotplug ownership. Firmware-first error
handling does not justify changing Slot Control after the native hotplug handoff.

The runtime log shows PDC on insertion, followed by successful NVMe
enumeration and queue setup.  A separate instrumented capture shows the
ISR returning early with cached HPIE clear.  These captures do not trace
the complete firmware/driver write sequence, so I should have made that
evidence boundary clearer in the commit message.

I will follow up with the firmware team on why the HPIE masking logic
runs with native hotplug enabled, and pursue a firmware-side correction.
Please hold off on this patch while we investigate that first.

Thanks,
Qiyu