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Sat, 26 Sep 2026 11:37:46 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-341447576b9sm18705762eec.15.2026.09.26.11.37.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 26 Sep 2026 11:37:45 -0700 (PDT) From: Taniya Das Date: Sun, 27 Sep 2026 00:07:10 +0530 Subject: [PATCH] clk: qcom: camcc-nord: Correct camera clock source tables Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260927-fix_camcc-v1-1-9fe956f01f6d@oss.qualcomm.com> X-B4-Tracking: v=1; b=H4sIANUQuGoC/6tWKk4tykwtVrJSqFYqSi3LLM7MzwNyDHUUlJIzE vPSU3UzU4B8JSMDIzMDSyMz3bTMivjkxNzkZF3zNANjAwvjZIOkZFMloPqColSgJNis6NjaWgC GV38OWwAAAA== X-Change-ID: 20260926-fix_camcc-7f03083c0bc5 To: Bjorn Andersson , Abel Vesa , Stephen Boyd , Brian Masney , Jerome Brunet , Konrad Dybcio , Dmitry Baryshkov Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , Shawn Guo , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das X-Mailer: b4 0.15-dev-aa3f6 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI2MDA3NCBTYWx0ZWRfX3EhEAhEro6tv IZAEaGJZQhpQV1Zxw3KmSax5WdRDouOs3C/my5qevYaJYouBG35gUGls0jDBeKQdgjl9yIXPKNS 9H6UcXEN8xqTN6NTnASDcW+L2LQKNPY= X-Authority-Analysis: v=2.4 cv=d8FgWhjE c=1 sm=1 tr=0 ts=6ab810fc cx=c_pps a=cFYjgdjTJScbgFmBucgdfQ==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=najPtik4V_E5PoWvo3cA:9 a=QEXdDO2ut3YA:10 a=scEy_gLbYbu1JhEsrz4S:22 X-Proofpoint-GUID: C3iR-VtmCDcW00_jjafKNB6BKrPPCoZL X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI2MDA3NCBTYWx0ZWRfX4MryJo1OjdPP z896XGw/SI6ePiM2OeezTM6GgOfXzDLBvbGVq/mLNKM49OvRXDSpyfYNeXEk/gDyEUz+v75x2BW Hs5UdcuvEWIoaDK1Hzi+GtPRDAzFPGcgnauVGb/Ab6zKCyFh1UGol+1BkbntcwPyu4VcALzuvZa tLW+e/17hIOmn1vFNVRCe3OOTXEkU8OU1NMKk8lJ7i8N9psEqDAgvaQEwY5YgcPWHfJGbsvK4VQ /2yuAWiVmcCcOQynDiFxaXzwu3C1Vgttf9OJD7/NYAQxW6EDgerkBF3Tb8EloDpgG3xoWw30nnY szcChUD2WcnIwIX9YL47Y0LqfO6b61inTS6StdxXIzoPoYviiiHEir8DTB7dBGWezMXPdE2KQXW bfdJyZS3CLBmxgN6l+eU2beq4t8sDGcOAwMthia17DHabGcckuky/79gYBg8IMpnUGLW7yJx54r jYl5zEtgjNlyht345pA== X-Proofpoint-ORIG-GUID: C3iR-VtmCDcW00_jjafKNB6BKrPPCoZL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 spamscore=0 priorityscore=1501 phishscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609260074 Select the PLL0 odd output for the 200 MHz and 400 MHz CAMNOC RT AXI rates. Use PLL0 main output dividers for the 300 MHz and 400 MHz CPHY RX rates. CSID and IFE Lite use the CPHY RX rates, so share that table rather than duplicating it. Remove the unsupported 300 MHz CSI PHY timer rate. Fixes: 7647815dfc8f ("clk: qcom: camcc: Add support for camera clock controller for Nord") Signed-off-by: Taniya Das --- drivers/clk/qcom/camcc-nord.c | 22 +++++++--------------- 1 file changed, 7 insertions(+), 15 deletions(-) diff --git a/drivers/clk/qcom/camcc-nord.c b/drivers/clk/qcom/camcc-nord.c index 9e3c40cb3ad5f06196bab87593afb7d1c7da411d..1c1314340b92f03af442b82a6402e442f1550a2c 100644 --- a/drivers/clk/qcom/camcc-nord.c +++ b/drivers/clk/qcom/camcc-nord.c @@ -515,8 +515,8 @@ static const struct clk_parent_data cam_cc_parent_data_9[] = { }; static const struct freq_tbl ftbl_cam_cc_camnoc_rt_axi_clk_src[] = { - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), + F(200000000, P_CAM_CC_PLL0_OUT_ODD, 2, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), { } }; @@ -622,8 +622,8 @@ static struct clk_rcg2 cam_cc_cci_4_clk_src = { }; static const struct freq_tbl ftbl_cam_cc_cphy_rx_clk_src[] = { - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), - F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), + F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), + F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), { } }; @@ -645,7 +645,6 @@ static struct clk_rcg2 cam_cc_cphy_rx_clk_src = { }; static const struct freq_tbl ftbl_cam_cc_csi0phytimer_clk_src[] = { - F(300000000, P_CAM_CC_PLL0_OUT_EVEN, 2, 0, 0), F(400000000, P_CAM_CC_PLL0_OUT_ODD, 1, 0, 0), { } }; @@ -730,19 +729,12 @@ static struct clk_rcg2 cam_cc_csi4phytimer_clk_src = { }, }; -static const struct freq_tbl ftbl_cam_cc_csid_clk_src[] = { - F(300000000, P_CAM_CC_PLL0_OUT_MAIN, 4, 0, 0), - F(400000000, P_CAM_CC_PLL0_OUT_MAIN, 3, 0, 0), - F(480000000, P_CAM_CC_PLL0_OUT_MAIN, 2.5, 0, 0), - { } -}; - static struct clk_rcg2 cam_cc_csid_clk_src = { .cmd_rcgr = 0x13214, .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csid_clk_src, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .hw_clk_ctrl = true, .clkr.hw.init = &(const struct clk_init_data) { .name = "cam_cc_csid_clk_src", @@ -889,7 +881,7 @@ static struct clk_rcg2 cam_cc_ife_lite_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csid_clk_src, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .hw_clk_ctrl = true, .clkr.hw.init = &(const struct clk_init_data) { .name = "cam_cc_ife_lite_clk_src", @@ -905,7 +897,7 @@ static struct clk_rcg2 cam_cc_ife_lite_csid_clk_src = { .mnd_width = 0, .hid_width = 5, .parent_map = cam_cc_parent_map_1, - .freq_tbl = ftbl_cam_cc_csid_clk_src, + .freq_tbl = ftbl_cam_cc_cphy_rx_clk_src, .hw_clk_ctrl = true, .clkr.hw.init = &(const struct clk_init_data) { .name = "cam_cc_ife_lite_csid_clk_src", --- base-commit: f5f84daefcd92d7a630066635ecea1433ed5eac7 change-id: 20260926-fix_camcc-7f03083c0bc5 Best regards, -- Taniya Das