Re: [PATCH v2 09/14] iio: adc: stm32: add support for vddgpu on stm32mp23 and stm32mp25

[Jonathan Cameron <jic23@kernel.org>]

On Wed, 23 Sep 2026 17:39:12 +0200
Fabrice Gasnier <fabrice.gasnier@foss.st.com> wrote:

> Add support for the vddgpu internal channel available on stm32mp23 and
> stm32mp25. It is enabled by using ADC2 and ADC3 option register. Add
> VDDGPU to the list of supported internal channels. Add sampling time
> information from the datasheet.
> 
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
I looked at everything before this point and only had comments
to add to Andy's existing review for patch 2.

You will need to rebase on the fix for v3.  That will probably
confuse Sashiko, so if you end up including that patch as
the first one in this series, add a clear note under the ---
that it is already applied.

Thanks,

Jonathan

> ---
> Changes in v2:
> - New patch split from V1, to avoid mixing new SoC / feature.
> ---
>  drivers/iio/adc/stm32-adc-core.h |  1 +
>  drivers/iio/adc/stm32-adc.c      | 18 ++++++++++++++++++
>  2 files changed, 19 insertions(+)
> 
> diff --git a/drivers/iio/adc/stm32-adc-core.h b/drivers/iio/adc/stm32-adc-core.h
> index 68b937e3819f..330c6c30e4f5 100644
> --- a/drivers/iio/adc/stm32-adc-core.h
> +++ b/drivers/iio/adc/stm32-adc-core.h
> @@ -273,6 +273,7 @@ enum stm32h7_adc_dmngt {
>  #define STM32MP25_RES_MASK		GENMASK(3, 2)
>  
>  /* STM32MP25_ADC23_OR - specific bit fields */
> +#define STM32MP25_VDDGPUEN		BIT(4)
>  #define STM32MP25_VDDCPUEN		BIT(3)
>  #define STM32MP25_VDDCOREEN		BIT(2)
>  
> diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
> index a14f858299ae..a2ed3abffa58 100644
> --- a/drivers/iio/adc/stm32-adc.c
> +++ b/drivers/iio/adc/stm32-adc.c
> @@ -97,6 +97,7 @@ enum stm32_adc_int_ch {
>  	STM32_ADC_INT_CH_VDDQ_DDR,
>  	STM32_ADC_INT_CH_VREFINT,
>  	STM32_ADC_INT_CH_VBAT,
> +	STM32_ADC_INT_CH_VDDGPU,
>  	STM32_ADC_INT_CH_NB
>  };
>  
> @@ -107,6 +108,7 @@ static const char stm32_adc_ic[STM32_ADC_INT_CH_NB][STM32_ADC_CH_SZ] = {
>  	[STM32_ADC_INT_CH_VDDQ_DDR] = "vddq_ddr",
>  	[STM32_ADC_INT_CH_VREFINT] = "vrefint",
>  	[STM32_ADC_INT_CH_VBAT] = "vbat",
> +	[STM32_ADC_INT_CH_VDDGPU] = "vddgpu"
>  };
>  
>  /**
> @@ -167,6 +169,7 @@ struct stm32_adc_vrefint {
>   * @smp_bits:		smpr1 & smpr2 index and bitfields
>   * @or_vddcore:		option register & vddcore bitfield
>   * @or_vddcpu:		option register & vddcpu bitfield
> + * @or_vddgpu:		option register & vddgpu bitfield
>   * @or_vddq_ddr:	option register & vddq_ddr bitfield
>   * @ccr_vbat:		common register & vbat bitfield
>   * @ccr_vref:		common register & vrefint bitfield
> @@ -186,6 +189,7 @@ struct stm32_adc_regspec {
>  	const struct stm32_adc_regs *smp_bits;
>  	const struct stm32_adc_regs or_vddcore;
>  	const struct stm32_adc_regs or_vddcpu;
> +	const struct stm32_adc_regs or_vddgpu;
>  	const struct stm32_adc_regs or_vddq_ddr;
>  	const struct stm32_adc_regs ccr_vbat;
>  	const struct stm32_adc_regs ccr_vref;
> @@ -725,6 +729,7 @@ static const struct stm32_adc_regspec stm32mp25_adc2_adc3_regspec = {
>  	.smp_bits = stm32h7_smp_bits,
>  	.or_vddcore = { STM32MP25_ADC23_OR, STM32MP25_VDDCOREEN },
>  	.or_vddcpu = { STM32MP25_ADC23_OR, STM32MP25_VDDCPUEN },
> +	.or_vddgpu = { STM32MP25_ADC23_OR, STM32MP25_VDDGPUEN },
>  	.ccr_vbat = { STM32H7_ADC_CCR, STM32H7_VBATEN },
>  	.ccr_vref = { STM32H7_ADC_CCR, STM32H7_VREFEN },
>  };
> @@ -953,6 +958,11 @@ static void stm32_adc_int_ch_enable(struct iio_dev *indio_dev)
>  			stm32_adc_set_bits_common(adc, adc->cfg->regs->ccr_vbat.reg,
>  						  adc->cfg->regs->ccr_vbat.mask);
>  			break;
> +		case STM32_ADC_INT_CH_VDDGPU:
> +			dev_dbg(&indio_dev->dev, "Enable VDDGPU\n");
> +			stm32_adc_set_bits(adc, adc->cfg->regs->or_vddgpu.reg,
> +					   adc->cfg->regs->or_vddgpu.mask);
> +			break;
>  		}
>  	}
>  }
> @@ -986,6 +996,10 @@ static void stm32_adc_int_ch_disable(struct stm32_adc *adc)
>  			stm32_adc_clr_bits_common(adc, adc->cfg->regs->ccr_vbat.reg,
>  						  adc->cfg->regs->ccr_vbat.mask);
>  			break;
> +		case STM32_ADC_INT_CH_VDDGPU:
> +			stm32_adc_clr_bits(adc, adc->cfg->regs->or_vddgpu.reg,
> +					   adc->cfg->regs->or_vddgpu.mask);
> +			break;
>  		}
>  	}
>  }
> @@ -2651,6 +2665,9 @@ static int stm32_adc_populate_int_ch(struct iio_dev *indio_dev, const char *ch_n
>  			case STM32_ADC_INT_CH_VBAT:
>  				na = !adc->cfg->regs->ccr_vbat.reg;
>  				break;
> +			case STM32_ADC_INT_CH_VDDGPU:
> +				na = !adc->cfg->regs->or_vddgpu.reg;
> +				break;
>  			default:
>  				return -EINVAL;
>  			}
> @@ -3160,6 +3177,7 @@ static const unsigned int stm32_adc_min_ts_mp25[STM32_ADC_INT_CH_NB] = {
>  	[STM32_ADC_INT_CH_VDDCPU] = 34,
>  	[STM32_ADC_INT_CH_VREFINT] = 34,
>  	[STM32_ADC_INT_CH_VBAT] = 34,
> +	[STM32_ADC_INT_CH_VDDGPU] = 34
>  };
>  
>  static const struct stm32_adc_cfg stm32mp23_adc1_cfg = {
>