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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2df91468978sm35292685ad.79.2026.09.27.23.37.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Sep 2026 23:37:17 -0700 (PDT) From: Anvesh Jain P Date: Mon, 28 Sep 2026 12:06:38 +0530 Subject: [PATCH 2/3] platform: arm64: qcom-hamoa-ec: Add thermistor sensors Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260928-ec_thermistor_support-v1-2-d9c1bae4cd0d@oss.qualcomm.com> References: <20260928-ec_thermistor_support-v1-0-d9c1bae4cd0d@oss.qualcomm.com> In-Reply-To: <20260928-ec_thermistor_support-v1-0-d9c1bae4cd0d@oss.qualcomm.com> To: Anvesh Jain P , Sibi Sankar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Hans de Goede , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Bryan O'Donoghue , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, platform-driver-x86@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790577422; l=4925; i=anvesh.p@oss.qualcomm.com; s=20260313; h=from:subject:message-id; bh=X9UFLy/tSfYGS4+J8pPMCA7NLf0Fczxwpqtp/69dYqY=; b=EPb/q5RPLAsViqDE6Uvnl/UuIaZ59tliKEnlPqYShFnn2utiQCbb41DjQPV4L0ttO5wzHdWu3 pQenjuz9uUJAGrnFAS1AwNr98t5Qzl81xNozVSLpMijAgqeGFBXxKFS X-Developer-Key: i=anvesh.p@oss.qualcomm.com; a=ed25519; pk=8o9EG7gkPe2Er9y9UVCx8MTdcFCwU8Pa54hBZPuduXE= X-Proofpoint-GUID: S5joydj1pQAO5A32sNXZEnJ6oLw9qdU8 X-Authority-Analysis: v=2.4 cv=C7F8WgP+ c=1 sm=1 tr=0 ts=6aba0b1f cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=iQKfIWaIXs3HRlposCEA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-ORIG-GUID: S5joydj1pQAO5A32sNXZEnJ6oLw9qdU8 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAyNiBTYWx0ZWRfX1hyK5Aw3wNKE 6AeurvLiZRWtMZVvz18+AUR7kx72hg/awkPlOXfQXWyiax7yr9jQbV7p52EQ+dcd3Qtb3IcwHQI 31qxsZ3eYZYbhVnHhWJUPOXyg3uY+1P+MHJKjTjh24BoaCC1mtdKErVGzEGWvnOktH0QmJrb4tW 0J78FDXT4SwtB1eu/vdGCGOgKzcBzg4sPfJYuKk1me47/qw6U1GwkzmpVMKGbZo7im9oKJ92xoW nFvD3xhgkGGOW7vPA7OCpQx814Ynd8O9o7YWELGQk3Nua6YHFD7vGlQLNEScxPgZXYgVpot/k1U x83lxAVoXBf/fFed6Wtq1rUCGbqKr+Le4g/8svWU3nQ7Dkdsy1KqxS+xmLbLBvWfaUH3Z9TVh+a HsJWcuBc6qoSqe8QJeSwrtDIjbhZsUamcU5nyYVQlsIwe/DSqdeVwPutxbOWSuPcH5d+53npcs5 mObLWTaLHMh6c62IYKg== X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAyNiBTYWx0ZWRfX7uoGwTHTnb+e CXx/AoFRl9+51B8aLxIVGf1BSa62diwmvlbn/MIuxFgboMVHVVzd1hI++qUqqvWqHwo6q4q/OXF 6MDPSObBdsBi8dvJvmloy/XgBneh4y8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 impostorscore=0 adultscore=0 suspectscore=0 spamscore=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280026 The Qualcomm embedded controller has exclusive access to multiple onboard thermistors programmatically discoverable through the EC_THERMAL_CAPABILITIES command. The temperature values are reported in degree Celsius through the EC_THERMISTOR_TEMP_CMD. Register these thermistors with the thermal framework by adding support to the EC_THERMISTOR_TEMP_CMD and convert it to millidegree units as required by the thermal framework. Signed-off-by: Anvesh Jain P --- drivers/platform/arm64/qcom-hamoa-ec.c | 74 ++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/platform/arm64/qcom-hamoa-ec.c b/drivers/platform/arm64/qcom-hamoa-ec.c index 4d2ad042a7f8..acf3d7f53026 100644 --- a/drivers/platform/arm64/qcom-hamoa-ec.c +++ b/drivers/platform/arm64/qcom-hamoa-ec.c @@ -16,16 +16,19 @@ #include #include #include +#include #define EC_SCI_EVT_READ_CMD 0x05 #define EC_FW_VERSION_CMD 0x0e #define EC_MODERN_STANDBY_CMD 0x23 +#define EC_THERMISTOR_TEMP_CMD 0x29 /* + thermistor_id (0-6) selects thermistor 1-7 */ #define EC_FAN_DBG_CONTROL_CMD 0x30 #define EC_SCI_EVT_CONTROL_CMD 0x35 #define EC_THERMAL_CAP_CMD 0x42 #define EC_FW_VERSION_RESP_LEN 4 #define EC_THERMAL_CAP_RESP_LEN 3 +#define EC_THERMISTOR_TEMP_RESP_LEN 3 #define EC_FAN_DEBUG_CMD_LEN 6 #define EC_FAN_SPEED_DATA_SIZE 4 @@ -39,6 +42,7 @@ #define EC_MAX_FAN_CNT 2 #define EC_FAN_NAME_SIZE 20 #define EC_FAN_MAX_PWM 255 +#define EC_MAX_THERMISTOR_CNT 7 enum qcom_ec_sci_events { EC_FAN1_STATUS_CHANGE_EVT = 0x30, @@ -64,6 +68,7 @@ struct qcom_ec_thermal_cap { #define EC_THERMAL_FAN_CNT(x) (FIELD_GET(GENMASK(1, 0), (x))) #define EC_THERMAL_FAN_TYPE(x) (FIELD_GET(GENMASK(4, 2), (x))) #define EC_THERMAL_THERMISTOR_MASK(x) (FIELD_GET(GENMASK(7, 0), (x))) +#define EC_THERMISTOR_PRESENT(mask, id) ((mask) & BIT(id)) u8 fan_cnt; u8 fan_type; u8 thermistor_mask; @@ -81,6 +86,12 @@ struct qcom_ec { struct qcom_ec_thermal_cap thermal_cap; struct qcom_ec_version version; struct i2c_client *client; + struct qcom_ec_thermal_zone *ec_tz; +}; + +struct qcom_ec_thermal_zone { + struct qcom_ec *ec; + u8 thermistor_id; }; static int qcom_ec_read(struct qcom_ec *ec, u8 cmd, u8 resp_len, u8 *resp) @@ -183,6 +194,43 @@ static int qcom_ec_thermal_capabilities(struct device *dev) return 0; } +/* + * EC Thermistor Temperature (cmd 0x29 + thermistor_id, id 0-6 selects + * thermistor 1-7): + * + * Read Response: + * ---------------------------------------------------------------------- + * | Offset | Name | Description | + * ---------------------------------------------------------------------- + * | 0x00 | Byte count | Number of bytes in response (=2) | + * ---------------------------------------------------------------------- + * | 0x01 (LSB)| Temperature | Signed 16-bit, unit of 0.1 degC, | + * | 0x02 (MSB)| | range -40..+125 degC | + * ---------------------------------------------------------------------- + */ +static int qcom_ec_thermistor_get_temp(struct thermal_zone_device *tz, int *temp) +{ + struct qcom_ec_thermal_zone *ec_tz = thermal_zone_device_priv(tz); + struct qcom_ec *ec = ec_tz->ec; + u8 resp[EC_THERMISTOR_TEMP_RESP_LEN]; + s16 raw; + int ret; + + ret = qcom_ec_read(ec, EC_THERMISTOR_TEMP_CMD + ec_tz->thermistor_id, + EC_THERMISTOR_TEMP_RESP_LEN, resp); + if (ret < 0) + return ret; + + raw = (s16)get_unaligned_le16(&resp[1]); + *temp = raw * 100; + + return 0; +} + +static const struct thermal_zone_device_ops qcom_ec_thermistor_ops = { + .get_temp = qcom_ec_thermistor_get_temp, +}; + static irqreturn_t qcom_ec_irq(int irq, void *data) { struct qcom_ec *ec = data; @@ -376,6 +424,32 @@ static int qcom_ec_probe(struct i2c_client *client) if (ret < 0) return dev_err_probe(dev, ret, "Failed to read thermal capabilities\n"); + if (ec->thermal_cap.thermistor_mask) { + ec->ec_tz = devm_kcalloc(dev, EC_MAX_THERMISTOR_CNT, sizeof(*ec->ec_tz), + GFP_KERNEL); + if (!ec->ec_tz) + return -ENOMEM; + + for (i = 0; i < EC_MAX_THERMISTOR_CNT; i++) { + struct qcom_ec_thermal_zone *ec_tz = &ec->ec_tz[i]; + struct thermal_zone_device *tzd; + + if (!EC_THERMISTOR_PRESENT(ec->thermal_cap.thermistor_mask, i)) + continue; + + ec_tz->ec = ec; + ec_tz->thermistor_id = i; + + tzd = devm_thermal_of_zone_register(dev, i, ec_tz, &qcom_ec_thermistor_ops); + if (IS_ERR(tzd)) { + ret = PTR_ERR(tzd); + if (ret != -ENODEV) + dev_warn(dev, "Failed to register thermistor%u zone: %d\n", + i, ret); + } + } + } + if (ec->thermal_cap.fan_cnt == 0) { dev_warn(dev, FW_BUG "Failed to get fan count, firmware update required\n"); return 0; -- 2.34.1