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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-87feaf8516esm3472936b3a.43.2026.09.27.22.30.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Sep 2026 22:30:53 -0700 (PDT) From: Sivansh Gupta To: Sibi Sankar Cc: Jassi Brar , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Sivansh Gupta Subject: [PATCH v3] mailbox: qcom-cpucp: read mbox hardware register using readq() Date: Mon, 28 Sep 2026 10:59:39 +0530 Message-ID: <20260928052940.688105-1-sivansh.gupta@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDAyMSBTYWx0ZWRfX5e64prPMUZcc nCw2S0abBT7Xi4Ie/w7xROC39EfYDFSChzdRz4YoENMhb3hv0X4W/hnwNroxLcv44htEZSSGgI/ 5YoGvE1bcAREtK8QwNPwseKHbaTu35A= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDAyMSBTYWx0ZWRfX3RZFvJiGnGID OmQm3Q3wFnWIbVr27bCXPDtITftP6zoM1nm1ZPtfcHcz2N2B0a+Pbw5M2zs/wDZNjq8ZreIpcGW 5r70laNCMkkEc3dysZfzQ4sodLK8sqOJqbyrvmIjC2ne9jed81St+oMHUfqft1k5tox69m982M8 VWnhT8YjzFlhq3coF3Tq9z2Fi8JJxcA88xhIM1frkz4ncA5wtWh/NzvRtERiSm5pbhvpnDLnaQi Lmzw5FppAHDXp+MlBdtZWcOFjKtMgMx/lIqkCYvo0gvUPkHy301Fx2smnZ/s8DU6QKv4rbLYUZL RUwyiu/FL3tJHBmIqR3rPU4EBU0KBop8VmA4qNrTwsN/ESM3YSe3xUmMC0uSFveZj4mg2gZ5LuY 0kPpwYsa9fyo708N7J7makV49BTRyJ5ZrBraSMpnOjUzEU1FHYbFuT4cZi5u+JixEV/wl0YVjoi 4D6O7dLdOfsEY3zPkSw== X-Proofpoint-ORIG-GUID: tMY8OUZKtBxMCj5AHfBciUiDY4lrpnkY X-Authority-Analysis: v=2.4 cv=E6xYNqdl c=1 sm=1 tr=0 ts=6ab9fb8e cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=zVvgFSUyQItoBg7ASCAA:9 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-GUID: tMY8OUZKtBxMCj5AHfBciUiDY4lrpnkY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-26_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280021 Mailbox hardware registers are 64 bit wide, but the interrupt handler currently reads only 32 bits with readl() at offset 0x4 (upper 32 bits). This returns an incorrect value, while reading using readq() returns the expected value. Use readq() to access the 64 bit register and pass the expected value to the mailbox client. Fixes: 0e2a9a03106c ("mailbox: Add support for QTI CPUCP mailbox controller") Signed-off-by: Sivansh Gupta --- v3: - Removed references to an out of tree driver to focus on the incorrect value returned by readl() https://lore.kernel.org/all/93ce8588-7500-45da-9b9a-424c202590cf@oss.qualcomm.com/#t v2: - Expanded the commit message to explain why this change is required. drivers/mailbox/qcom-cpucp-mbox.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mailbox/qcom-cpucp-mbox.c b/drivers/mailbox/qcom-cpucp-mbox.c index 862e45e8fbd5..0b584d9aad6c 100644 --- a/drivers/mailbox/qcom-cpucp-mbox.c +++ b/drivers/mailbox/qcom-cpucp-mbox.c @@ -61,7 +61,7 @@ static irqreturn_t qcom_cpucp_mbox_irq_fn(int irq, void *data) status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT); for_each_set_bit(i, (unsigned long *)&status, cpucp->mbox.num_chans) { - u32 val = readl(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i) + APSS_CPUCP_MBOX_CMD_OFF); + u64 val = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_CMD(i)); struct mbox_chan *chan = &cpucp->chans[i]; unsigned long flags; -- 2.43.0