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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2dbed87650sm291164166b.50.2026.09.28.07.32.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2026 07:32:10 -0700 (PDT) From: Andrew Jones To: iommu@lists.linux.dev, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: tomasz.jeznach@linux.dev, jgg@ziepe.ca, jgg@nvidia.com, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com, tglx@kernel.org, anup@brainfault.org, atish.patra@linux.dev, fangyu.yu@linux.alibaba.com, zhangzhanpeng.jasper@bytedance.com, zong.li@sifive.com Subject: [RFC PATCH v3 08/14] irqchip/riscv-imsic: Define IOMMU IRQ bypass protocol Date: Mon, 28 Sep 2026 16:31:07 +0200 Message-ID: <20260928143113.49838-9-andrew.jones@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260928143113.49838-1-andrew.jones@oss.qualcomm.com> References: <20260928143113.49838-1-andrew.jones@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 2u3fl74SDO9E6i7aIRtwRv3p8t73wFtR X-Proofpoint-ORIG-GUID: 2u3fl74SDO9E6i7aIRtwRv3p8t73wFtR X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI4MDA1OSBTYWx0ZWRfXy/JxyGosdD/D K/ugEgnXRPjzLtyfyZaNdaR1N/MeyYcNC55QyS2UUWWRHnHJkV39gCBdj1zkrWr5yrbfzFijF98 9f+DvbLFd+xgxmIRIdY2F0A+YfoRc20= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI4MDA1OSBTYWx0ZWRfX2ESeZuocTBx8 ZqXBKG3F248uOsax3LP/bcg1alQB2/3HatxiUegHRAFWphErZp64NdP49rTj6ZD/5i9+iXZyQIb agggk0cHOUCRPy2pU/b6sC0f3cc1cjTbAh7+oQxcmB+gUqGrAjBkNboaZDlRfWgeHK1Lb683PiV F8ay+PixqCJCpSz6YkyXIW7JGh9Gh7BLVu5nE1Z9HXM+v7UQMGg8MyMROKhKOYCQJHdQiwSh/Fm Orw4+/JpU9EV9XTzMuSs9VJYSgvZE2EEbcHY9o4K96lnblX1qiDQoDueWUXNRxVwuTA2R/DuQN4 vffdEAjyew5vMru2BFVZQw8+/wwCe3lmuRzUZ+lfa3jtpHpP6JqnmL9bGCUxUsCx0X+UF45mmAf OYt++zEX221chqKALd2FnGtYpuD/IHEdoUqpGKf7fiY8vifDA4/T0861XyUadbNHIibEnHHSSba /SVurnFI0BMwKHdEAtw== X-Authority-Analysis: v=2.4 cv=QZfzLcbv c=1 sm=1 tr=0 ts=6aba8179 cx=c_pps a=ngMg22mHWrP7m7pwYf9JkA==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=4AuT_VmNVbg3FCPyVe8A:9 a=yHXA93iunegOHmWoMUFd:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-28_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 priorityscore=1501 phishscore=0 impostorscore=0 suspectscore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609280059 Define the RISC-V IOMMU payload for irq_set_vcpu_affinity(), including domain-wide target setup and individual target updates for IMSIC and MRIF targets. Signed-off-by: Andrew Jones --- include/linux/irqchip/riscv-imsic.h | 52 +++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h index 662cb0442424..d024a6524baa 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -104,4 +104,56 @@ struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev); static inline struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev) { return NULL; } #endif +enum riscv_iommu_ir_cmd { + RISCV_IOMMU_IR_INVALID_CMD, + RISCV_IOMMU_IR_FORWARD, + RISCV_IOMMU_IR_UPDATE_TARGET, +}; + +enum riscv_iommu_ir_target_type { + RISCV_IOMMU_IR_TARGET_INVALID, + RISCV_IOMMU_IR_TARGET_IMSIC, + RISCV_IOMMU_IR_TARGET_MRIF, +}; + +struct riscv_iommu_ir_target { + u64 gpa; + enum riscv_iommu_ir_target_type type; + union { + u64 hpa; + struct { + u64 mrif_hpa; + u64 notice_hpa; + u32 notice_id; + }; + }; +}; + +/* + * FORWARD enables forwarding for one IRQ and provides the complete target array + * so the first forwarded IRQ can initialize the domain MSI table. UPDATE_TARGET + * replaces one target without changing per-IRQ forwarding state. The caller + * must quiesce all MSI producers using the table when changing both words of a + * live MRIF PTE because the update temporarily invalidates the entry. A NULL + * vcpu_info disables forwarding for the IRQ. + * + * A well-formed request which is incompatible with the producer or current + * domain configuration returns -EOPNOTSUPP, allowing the caller to fall back + * to host delivery. Invalid payloads return -EINVAL and operational errors are + * propagated. + */ +struct riscv_iommu_ir_vcpu_info { + enum riscv_iommu_ir_cmd cmd; + const void *owner; + u64 msi_addr_mask; + u64 msi_addr_pattern; + union { + struct { + const struct riscv_iommu_ir_target *targets; + unsigned int nr_targets; + }; + struct riscv_iommu_ir_target target; + }; +}; + #endif -- 2.43.0