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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BN3PEPF0000B372.mail.protection.outlook.com (10.167.243.169) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.496.3 via Frontend Transport; Mon, 28 Sep 2026 18:09:53 +0000 Received: from airavat.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Mon, 28 Sep 2026 13:09:50 -0500 From: Vishal Badole To: , , , , CC: Vishal Badole Subject: [PATCH v2 0/2] EDAC/amd64: Fix UMC csrow decode and consolidate Family 1Ah setup Date: Mon, 28 Sep 2026 23:39:33 +0530 Message-ID: <20260928180935.472319-1-Vishal.Badole@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B372:EE_|MN2PR12MB4189:EE_ X-MS-Office365-Filtering-Correlation-Id: 2ce8fe1f-99d3-439b-25cc-08df1d8bb21e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|23010399003|36860700016|1800799024|376014|10067099003|11063799006|56012099006|18002099003|13003099007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bHFpxzMPTUDjVvCgY4tF0ypNqilJYUFdCNemw1RmcJcZXzHixn67MPQ2Qy/UWMfEULI72I37k25yQnF5UALaJUZb44PxBM0u/8PrLMqucB2ZFqbORToa8fg/2IdWq425wd7glVv8x85sQ5AE+QzBxDgGjFJRNHYfmdzbpyNKXKIwYs4psL0x8U0UGFODpJHKdDuP4ZnfCAeyfXhYxoOQUThyfDaLnRzXWdWfY9+mdKj7Qm+GE5iuninbzgtHHyN3j0aDLDKxsQmOuumwS+bHxQ5unCC0Iqs69IzyOLuCI+QapZlOdq+9hRH+i6o29CUSxRqofSAYWHih/OCHOEAVmlr/CJnjh8+FWyMuthYH7wjQksUyeSLq0gztCRhv/6zJ3qkvPKmR2uG5181LUtQu5hEDRToCk84g8pQ4iA33hlR1OD21R/wMeU9pkRF84kVL X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 18:09:53.5402 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2ce8fe1f-99d3-439b-25cc-08df1d8bb21e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B372.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4189 Two small amd64_edac fixes/cleanups for AMD Family 1Ah. Patch 1 is the fix: mask the UMC chip select with 0x3, not 0x7. Only four chip selects exist, so the old mask could decode an out-of-range csrow and trip an EDAC warning. Patch 2 sets zn_regs_v2 once at the Family 1Ah level instead of in each model case, so future models cannot miss the v2 register layout. Changes since v1: - Patch 1 (fix): Added Fixes: and Cc: stable, and move the fix first. - Patch 2 (cleanup): Updated the commit message. v1: https://lore.kernel.org/all/20260925172639.97063-1-Vishal.Badole@amd.com/ Vishal Badole (2): EDAC/amd64: Mask UMC chip select to the four implemented selects EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models drivers/edac/amd64_edac.c | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) -- 2.34.1