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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?86l4TikYjnkU2RZeb1g87XQTVefG2mGZBKkUtJ56u/sTh78NMYEIE3jxGLex?= =?us-ascii?Q?qTz734V3RXi0b4Z/doiFiG/i3KVhhMC2oZXtsLpdDCOnK8CVBtXW4X363P8u?= =?us-ascii?Q?9KwLSzQXMIe7mP4Xi3TBT2/UDfdL+7OtzUJEVo0fQ0HZlvApLpXSFLX8XWMo?= =?us-ascii?Q?3DntEtLAuLLUMl287Teu3crxmqyGvQmHNWrRORRJ/UHWPGrzVzd2iMdx63eX?= =?us-ascii?Q?rPG3mGt46oWhlrN21p1C9fnOPp+D7++oPONjZiY5wNQeXgtkJnnOdT/9xxJ5?= =?us-ascii?Q?gE+aTlFac48Y8GNHj2XjkGh/1T62/CaW2b41hX1VUp2SBHic4N5cfkOZLt41?= =?us-ascii?Q?oWr2y4Ie6OY4/9je27A6vBYVUKdcpvctZF1nZeSEjJgNSk++BXXerEpH10Z5?= =?us-ascii?Q?MWxHyogWYxmaUozYfuhdeFaAOpgJ//aXC3+233giy5RlMGQLrJ4jwPFVYKcu?= =?us-ascii?Q?Kn3cfFrDZjAvC1VSVvxs+dEzutShYDPxh1GEGevCIcYO9c87Jseeg9R57G2u?= =?us-ascii?Q?YeYki7Dc4H7uAoPY4ckTIwZq/uhLqzXJahxgu9wldMrjjn8ueeiunPno25jS?= =?us-ascii?Q?sXlim6YMi/GUWQMQbNjT7oh719NWbFylNgZX5vQM69iBWI1MMhSZF66NCsy/?= =?us-ascii?Q?MmlNan8nIBllkaXCCw1g/RxILBueUQO/3fLcZbJ2Nncx0yv/9h2DQuMyVy+1?= =?us-ascii?Q?6zFGVt3QrlUvFMWbTx/wKlVWK8glP1BVL0+DSeC6rIrv1eHHUS2G3COSQWCC?= =?us-ascii?Q?wYeKPXGmC94x3yBmv5gUt3/COFI+t61rT0VtCuum+lv6Q+FI5BPGh7lVqCkT?= =?us-ascii?Q?uD9US+RKCuOtMyoebzZcZySwuGE9wxtUAPyPq7TJsz5foHrY9l0BLX8CcWmv?= =?us-ascii?Q?Qg7SmEmzNMom+Hx0R03LJeoJ4uunkKzjiREFVUgRfq4opgmNhdXlFECVWlVm?= =?us-ascii?Q?q1ZIbu/ejI2SvU+0SY4EQjNP/Cw4N0tei8gI1mGc+jNGX37drm9/ZyQbtue0?= =?us-ascii?Q?onWX+hlFmJqybSZzpc3T+hbxqFGB7GsUZqAaiF6F7tk+/LB3M0b+9nvHnYRk?= =?us-ascii?Q?VRDHaxXfyIVGv4pL31Ej7aRRMHACRULxEfH2voaH3dw6dNRIJp8ALwnxcC+b?= =?us-ascii?Q?oVkofrRSycJeiYozFCJEBz4yqXqJCd3U3/iw+8OufaJ1lVkQdeC/O+6aDCob?= =?us-ascii?Q?H6WZ6UKSuFZcwfvvOgFfHQ8cak+h4wZ1k/I/1uvv+3EMcZhzpgXHfc105GGO?= =?us-ascii?Q?dLsl+BQfsAlXK7l1K2BCFVCUKdYsjrlxBT0G0l4lH7mk7QGF7/u0TabUYwt0?= =?us-ascii?Q?Txx2oZhV3zjGw5hX2JBMuc5ZAR33JOLMqUQgNd7wQT//Sy6DkRS9AjH8d4Q1?= =?us-ascii?Q?Ekup+lTDE2JwiZvuEfAfTz/T9+uqJLD8X7ntTWjJIa+6PGfJ0RaQJAIyLlxk?= =?us-ascii?Q?YMW5CPYu7i1qvOsd2ha4dFNdxWo/cYEmT/oOqg5/cNpG2hGCnE3Xi98JXHKD?= =?us-ascii?Q?AHiS7aMSWcsc+7ZrzM81JfDmOYT6C0p9od248StH5HdafJZ1T12byGCkqtMl?= =?us-ascii?Q?vp2u+d4apspAq/zu8n1ujPOc8mdbAYPA6Yy++fDVMvOQvzNEXU9rIS/oOvkj?= =?us-ascii?Q?0nQtar/AIG8eMxhOvDR1wvzWYPJ0Q31e0ZA/oTGC5ySNhlTH5exQaEAwvyzq?= =?us-ascii?Q?+ZVU9I78h5MSLtKbRPWPCmYww/w5FR2tq+KyJ/LkxhAKDm42?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f36dd8cd-6c73-4154-9e57-08df1da1928d X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6374.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 20:46:29.7297 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: t/6/fz3G5e5VpiTlQjg1dbKOnfpF+QIl654KWvnAAjnfDbJapeQHnnA4fkQe2Wwf0FPw7Rp8rDxJGb6Ky92vCw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB8929 On Mon, Sep 28, 2026 at 11:39:34PM +0530, Vishal Badole wrote: > umc_get_err_info() masks the Chip Select from MCA_SYND with 0x7, a > leftover from Zen 1 where the architecture reserved space for up to > eight chip selects. Only four have ever been implemented, and newer > products document this as MCA_SYND_UMC[1:0] = Chip Select. > > Since only four csrows are allocated, a syndrome with bit 2 set decodes > to an out-of-range csrow and trips: > > EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4) > > Mask with 0x3 to match the four implemented chip selects. > Here's an alternate commit message. Hopefully, this clears up some of the points from Boris in the other thread. Thanks, Yazen ======================================= For DRAM ECC errors, the chip select value can be found in the MCA_SYND[ErrorInformation] field. ErrorInformation[2:0] was first documented in Zen1. The 3 bit field implied that up to 8 chip selects may be used. However, all Zen-based systems have only ever had up to 4 chip selects. So only bits [1:0] would contain a valid chip select value. Future systems are redefining the field to ErrorInformation[1:0]. This matches the existing 'up to 4 chip selects' implementations. And it frees up the extra bit for other decoding. Change the current chip select mask from 0x7 to 0x3 to prepare for the decode change.