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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , George Moussalem , Ziyang Huang , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH net v2 0/2] net: phy: qcom: at803x: IPQ5018 analog initialization fixes Date: Tue, 29 Sep 2026 00:07:15 +0200 Message-ID: <20260928220717.939-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit When the IPQ5018 internal GE PHY is connected to another PHY without a cable, its analog setup matters for the 1000BASE-T link. Two problems in that setup are fixed here. Patch 1 fixes the short-cable DAC values, which were written to the wrong bits. It is the patch sent as v1 [1], unchanged except for Andrew's Reviewed-by. Patch 2 applies the analog settings in probe, right after the PHY reset, instead of only when the MAC attaches the PHY. The PHY starts autonegotiating when it leaves reset, so until attach it negotiated with its reset defaults. On a Redmi AX5400, where it connects to PHY4 of a QCA8337, 1000BASE-T never came up in that state and SmartSpeed on the switch PHY dropped its 1000BASE-T advertisement for good. With patch 2 the link came up at 1 Gb/s with SmartSpeed left enabled, and the SmartSpeed workaround discussed in [2] is no longer needed. On that board, with both patches backported to OpenWrt's Linux 6.18.52, the link was verified at 1 Gb/s after a first boot, three reboots, a power-off cold boot, interface down/up cycles, renegotiations and a network restart. During a separate 10-minute observation, sampled link status remained at 1 Gb/s and no new switch-side CPU PHY link-down events were logged. After the cold boot the switch side first reported 1 Gb/s at 4.4 s; it went down at MAC attach and recovered at 25.2 s. Patch 2 accesses the PHY right after reset_control_reset(), which pulses GCC_GEPHY_MISC_ARES for about 1 us. The vendor SDK waits 200 ms after deasserting each Ethernet reset, but it does so for every block alike, so that does not establish a GE PHY-specific minimum delay. This patch adds no post-reset delay. Diagnostic warm-boot tests on this board read back the values correctly after writing them in probe. I have no specification for the required post-reset interval. George, does the GE PHY require a minimum delay or a readiness check after ARES is deasserted, before its analog settings are written and autonegotiation is restarted? Thanks to Ziyang Huang for asking whether the DAC settings had been corrected [3], which is how the first problem was found, and to Andrew Lunn for his reviews in the v3 thread, which kept the investigation going until the cause was found. Changes since v1: - Added patch 2. - Patch 1: added Andrew's Reviewed-by and Ziyang's Suggested-by. [1] https://lore.kernel.org/netdev/20260927155136.2489-1-yongzhao.derek@gmail.com/ [2] https://lore.kernel.org/netdev/20260923215858.1653-1-yongzhao.derek@gmail.com/ [3] https://lore.kernel.org/netdev/SEYPR01MB58827E0D18ACC93AF98A4109C98E2@SEYPR01MB5882.apcprd01.prod.exchangelabs.com/ Yongzhao Chen (2): net: phy: qcom: at803x: Fix IPQ5018 short-cable DAC values net: phy: qcom: at803x: Apply IPQ5018 analog settings at probe drivers/net/phy/qcom/at803x.c | 94 ++++++++++++++++++++++++++--------- 1 file changed, 70 insertions(+), 24 deletions(-) base-commit: a7bfaba4823e3c165bb2004c74eff7c096672bc7 -- 2.43.0