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Mon, 28 Sep 2026 12:45:54 -0700 Received: from inno-dell (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Mon, 28 Sep 2026 12:45:47 -0700 Date: Mon, 28 Sep 2026 22:45:45 +0300 From: Zhi Wang To: Danilo Krummrich CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Peter Colberg Subject: Re: [PATCH v2 1/8] rust: pci: add {enable,disable}_sriov(), to control SR-IOV capability Message-ID: <20260928224545.78fcea51@inno-dell> In-Reply-To: References: <20260924190556.1620886-1-zhiw@nvidia.com> <20260924190556.1620886-2-zhiw@nvidia.com> X-Mailer: Claws Mail 4.3.1 (GTK 3.24.52; x86_64-pc-linux-gnu) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000A893:EE_|CH2PR12MB9542:EE_ X-MS-Office365-Filtering-Correlation-Id: d9227a6e-275c-41d7-e160-08df1d99298f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|7416014|23010399003|376014|1800799024|82310400026|6133799003|10067099003|11063799006|56012099006|4143699003|22082099003|18002099003|3023799007; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: TgOUx8wu78LCmwNByhwMlDz7Ji0wutGxbhASCYDMmMB6KlF5R1HK0IxHgRVi8t59ZQWz9FuPWgHZ17rgl8I7HTZKiYStz+b4nYz+wQvBpU0R781ij2UCYxAtyCGdTKbY2QwlB+3GQkKoISAv6kCZQuGvrIqbHyMVwxAk9UQXcp2UDv9HkKMDYCf61NYfZF4lRfGBnXSLHpGkKr8KEUc9/ffi4P7d2HzTkgMxvDOXq4ri51SYzdMSMiy730mH/IcaCGAT23rOfMpiRdIACrpZUa7qxJ4vOoS1LalXRdI2+mU/qNYvcBcrx/1Xy2rs9U6X0NItkQhGZLi5+Ytc9P1sdbLALutOM8xqVJj+ZoHtDzmxQLAVxNwOACSE4bdZyTv2EJLfa1mvRNyiaxeVflySr2YAnhs4EPeK6sir5U80TJBrR2cgfuFOJhnc/I/CE3aO X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2026 19:46:17.2526 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d9227a6e-275c-41d7-e160-08df1d99298f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000A893.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB9542 On Sun, 27 Sep 2026 18:37:06 +0200 "Danilo Krummrich" wrote: > On Thu Sep 24, 2026 at 9:05 PM CEST, Zhi Wang wrote: > > diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs > > index 3ec897709e89..e6dac919f02d 100644 > > --- a/rust/kernel/pci.rs > > +++ b/rust/kernel/pci.rs > > @@ -133,6 +133,10 @@ extern "C" fn remove_callback(pdev: *mut > > bindings::pci_dev) { // INVARIANT: `pdev` is valid for the duration > > of `remove_callback()`. let pdev = unsafe { > > &*pdev.cast::>>() }; > > + // Keep PF data installed until all VF remove callbacks > > have completed. > > + #[cfg(CONFIG_PCI_IOV)] > > + pdev.disable_sriov(); > > I don't think we need this? The VfRegistration should guard against > this already. > Nice catch. This was already handled in the VfRegistration. > > + > > // SAFETY: `remove_callback` is only ever called after a > > successful call to // `probe_callback`, hence it's guaranteed that > > `Device::set_drvdata()` has been called // and stored a > > `Pin>>`. @@ -472,6 +476,38 @@ pub fn > > set_master(&self) { // SAFETY: `self.as_raw` is guaranteed to be a > > pointer to a valid `struct pci_dev`. unsafe { > > bindings::pci_set_master(self.as_raw()) }; } > > + snip > > } > > I think we do not need to expose those as functions on Device. > We should only need to call those from the sriov_configure() callback > and should otherwise be covered by the VfRegistration. > > Hence, I suggest to expose those methods via a token type, which also > helps to use an RAII patterns for cleanup rather than manual > enable/disable calls: > I see. With this, if something unexpected happens during the sriov_enable callback in driver setup, the sriov_disable can be automatically called then. Let me slightly change this patch to expose the functions in Device and add a new patch for the below idea. Z. > Instead of a single sriov_configure() callback that covers both > cases, we can have two callbacks. > > fn sriov_enable<'bound>( > dev: &'bound Device>, > data: Pin<&'bound Self::Data<'bound>>, > token: SriovEnable<'_>, > ) -> Result>; > > and > > fn sriov_disable<'bound>( > dev: &'a Device>, > data: Pin<&'bound Self::Data<'bound>>, > token: SriovDisable<'_>, > ) -> Result; > > Note the return type on sriov_enable(), which is obtained from > token.enable(). It can serve as guard and automatically disable again > of sriov_enable() fails subsequently and returns an error. If it > successfully returns SriovEnabled, the PCI core can just discard it. > The structs could look like this: > > pub struct SriovEnable<'a> { > dev: &'a Device>, > num_vfs: u32, > } > > impl<'a> SriovEnable<'a> { > pub fn num_vfs(&self) -> u32 { > self.num_vfs > } > > pub fn enable(self, num_vfs: u32) -> > Result> { let ret = unsafe { > bindings::pci_enable_sriov(self.dev.as_raw(), > num_vfs) }; > to_result(ret)?; > > Ok(SriovEnabled { dev: self.dev, num_vfs }) > } > } > > And the destructor of SriovEnabled could be: > > impl Drop for SriovEnabled<'_> { > fn drop(&mut self) { > unsafe { > bindings::pci_disable_sriov(self.dev.as_raw()) } } > } > > We could still have the helpers on Device so you can > use them safely in the guard types. Got it.