From: Loic Poulain <loic.poulain@oss.qualcomm.com>
To: Robert Foss <rfoss@kernel.org>,
Andi Shyti <andi.shyti@kernel.org>,
Wolfram Sang <wsa+renesas@sang-engineering.com>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Luca Weiss <luca@lucaweiss.eu>
Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, vladimir.zapolskiy@linaro.org,
konradybcio@kernel.org, stephan.gerhold@linaro.org,
Loic Poulain <loic.poulain@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH v6 3/5] i2c: qcom-cci: Add 19.2 MHz timings for the v2 CCI
Date: Tue, 29 Sep 2026 14:25:47 +0200 [thread overview]
Message-ID: <20260929-cci-clk-fix-v6-3-62a268cccb0f@oss.qualcomm.com> (raw)
In-Reply-To: <20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com>
The v2 CCI (msm8996/sdm630/msm8953/...) is normally clocked at 37.5 MHz,
but its CCI clock can also be configured and run at 19.2 MHz. Add the
Standard and Fast timing sets calibrated for 19.2 MHz so that a v2
controller left at that rate still has valid timings for those modes
(Fast+ requires 37.5 MHz).
The values mirror the v1/v1.5 19.2 MHz Standard/Fast timings, which
share the same CCI clock rate.
Note the "v1"/"v1.5"/"v2" labels are arbitrary driver-internal names for
the cci_data configs, not actual CCI hardware version numbers (the real
hw versions are e.g. v1.0.7 on msm8974, v1.4.0 on msm8996, v1.6.3 on
sdm630/660, ...). They only distinguish the timing/mode configurations
used by the driver, and will be subsequently removed.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
---
drivers/i2c/busses/i2c-qcom-cci.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c
index 1092ce0371429ef64c7cc44cc23a42ba4c135af5..b6fa37a306758ec33ede6fcc39ce4412b86d9a84 100644
--- a/drivers/i2c/busses/i2c-qcom-cci.c
+++ b/drivers/i2c/busses/i2c-qcom-cci.c
@@ -762,6 +762,30 @@ static const struct cci_data cci_v2_data = {
.max_write_len = 11,
.max_read_len = 12,
},
+ .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_STANDARD] = {
+ .thigh = 78,
+ .tlow = 114,
+ .tsu_sto = 28,
+ .tsu_sta = 28,
+ .thd_dat = 10,
+ .thd_sta = 77,
+ .tbuf = 118,
+ .scl_stretch_en = 0,
+ .trdhld = 6,
+ .tsp = 1
+ },
+ .params[CCI_CLK_RATE_19_2MHZ][I2C_MODE_FAST] = {
+ .thigh = 20,
+ .tlow = 28,
+ .tsu_sto = 21,
+ .tsu_sta = 21,
+ .thd_dat = 13,
+ .thd_sta = 18,
+ .tbuf = 32,
+ .scl_stretch_en = 0,
+ .trdhld = 6,
+ .tsp = 3
+ },
.params[CCI_CLK_RATE_37_5MHZ][I2C_MODE_STANDARD] = {
.thigh = 201,
.tlow = 174,
--
2.34.1
next prev parent reply other threads:[~2026-09-29 12:26 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-29 12:25 [PATCH v6 0/5] i2c: qcom-cci: Enforce the required CCI clock rate Loic Poulain
2026-09-29 12:25 ` [PATCH v6 1/5] i2c: qcom-cci: Switch msm8953 to the CCI v2 timing/rate config Loic Poulain
2026-09-29 12:25 ` [PATCH v6 2/5] i2c: qcom-cci: Support per-mode CCI clock rates Loic Poulain
2026-09-29 12:25 ` Loic Poulain [this message]
2026-09-29 12:25 ` [PATCH v6 4/5] i2c: qcom-cci: Share the timing table across CCI revisions Loic Poulain
2026-09-29 12:25 ` [PATCH v6 5/5] i2c: qcom-cci: Enforce the required CCI clock rate Loic Poulain
2026-10-05 10:08 ` [PATCH v6 0/5] " Andi Shyti
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