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Tue, 29 Sep 2026 06:49:06 +0000 From: haibo.chen@oss.nxp.com Date: Tue, 29 Sep 2026 14:53:07 +0800 Subject: [PATCH v2] mtd: spi-nor: clear the default RDCR opcode when entering Octal DTR Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260929-spi-nor-fix-v2-1-75440cfe4e76@nxp.com> X-B4-Tracking: v=1; b=H4sIAFJgu2oC/22MQQ6CMBAAv0L27JqyURBP/MNwaMsie7BtWtNgS P9u5exxJpnZIXEUTnBvdoicJYl3FejUgF21ezLKXBlIUacGumEKgs5HXGRDNj0bJtL9RUEtQuS qj9tjqrxKevv4Oea5/dn/n9xii5a7q9GDsouZR7eFs/UvmEopXwol03+kAAAA X-Change-ID: 20260928-spi-nor-fix-eb7ebe22a740 To: Pratyush Yadav , Michael Walle , Takahiro Kuwano , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, michael@walle.cc, Haibo Chen X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1790664813; l=2783; i=haibo.chen@nxp.com; s=20250421; h=from:subject:message-id; bh=yt9wzN6CH0kwWTN44oiWIwDb7Ww7u5Z5wLSssQtm5CY=; b=ecA5g14RQWxvBKxl5lyVm7pOf5t4yuWTXmidGjlglZiILEyPvTS2H38mx1sp9CN6POU3l4NYF X5K94MWs81rCG6mBPhyvHHaeVCFv4HTAb0gsaNOJBP2tYFBBWKE97s0 X-Developer-Key: i=haibo.chen@nxp.com; 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In 8D-8D-8D mode the opcode is extended to two bytes per cmd_ext_type, but the resulting command is not a valid SR2 read for these flashes, which access their status/config registers through a vendor-specific indirect register space. Since spi_nor_cache_sr_lock_bits() now reads SR2 during init, i.e. after the switch to Octal DTR, the extended RDCR gets no data back and the read times out (on i.MX FlexSPI: -ETIMEDOUT and a controller WARN() during probe with Micron MT35xU and Macronix octal parts). Clear read_sr2 when the switch to Octal DTR actually succeeds, so the SR2 read is skipped (a cleared opcode already means "unsupported"). Doing it in spi_nor_set_octal_dtr() keys off the real runtime protocol: a flash that advertises Octal DTR but runs in (x)STR because the host lacks support keeps its usable RDCR. Assisted-by: LLM Fixes: b7b63475903c ("mtd: spi-nor: Create a local SR cache") Fixes: 63489002d397 ("mtd: spi-nor: Refactor Read Status/Write Status support") Signed-off-by: Haibo Chen --- Changes in v2: - Rework the fix following review: instead of guarding the read at runtime in spi_nor_read_sr2(), clear the default RDCR opcode.read_sr2 once, at the point the switch to Octal DTR succeeds (spi_nor_set_octal_dtr()). - Key the clear off the real runtime protocol so a flash that advertises Octal DTR but runs in (x)STR (host without 8D support) keeps its RDCR. - Drop the swp.c change and the -EOPNOTSUPP handling; a cleared read_sr2 already means "no SR2 read", handled by the existing debugfs caching path. - Trim the code comment; move the details to the commit message. - Link to v1: https://lore.kernel.org/r/20260928-spi-nor-fix-v1-1-ce65ba90cfbd@nxp.com --- drivers/mtd/spi-nor/core.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c index 90524c58602e1c27cd83951ab0cdd3669a2ebfd6..5c0985491ade59cab317b74aab8572d7caedb64a 100644 --- a/drivers/mtd/spi-nor/core.c +++ b/drivers/mtd/spi-nor/core.c @@ -3014,10 +3014,16 @@ static int spi_nor_set_octal_dtr(struct spi_nor *nor, bool enable) if (ret) return ret; - if (enable) + if (enable) { nor->reg_proto = SNOR_PROTO_8_8_8_DTR; - else + /* + * The default RDCR is not a valid SR2 read in Octal DTR mode; + * clear it so SR2 reads are skipped instead of being issued. + */ + nor->params->opcodes.read_sr2 = 0; + } else { nor->reg_proto = SNOR_PROTO_1_1_1; + } return 0; } --- base-commit: ba52b770f89bd2f3771b98edb92c4fde68ca8cc4 change-id: 20260928-spi-nor-fix-eb7ebe22a740 Best regards, -- Haibo Chen