From: phucduc.bui@gmail.com
To: Mark Brown <broonie@kernel.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Darren Ye <darren.ye@mediatek.com>
Cc: Liam Girdwood <lgirdwood@gmail.com>,
Matthias Brugger <matthias.bgg@gmail.com>,
Jaroslav Kysela <perex@perex.cz>, Takashi Iwai <tiwai@suse.com>,
cassiogabrielcontato@gmail.com,
Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>,
Liviu Dudau <liviu.dudau@arm.com>,
Cyril Chao <Cyril.Chao@mediatek.com>,
linux-sound@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org,
bui duc phuc <phucduc.bui@gmail.com>
Subject: [PATCH 01/10] ASoC: mediatek: mt8196: fix APLL mux error handling
Date: Tue, 29 Sep 2026 13:11:12 +0700 [thread overview]
Message-ID: <20260929061121.124001-2-phucduc.bui@gmail.com> (raw)
In-Reply-To: <20260929061121.124001-1-phucduc.bui@gmail.com>
From: bui duc phuc <phucduc.bui@gmail.com>
Propagate errors from clock operations in the enable path and clean up
previously enabled clocks when a later operation fails.
For the disable path, continue disabling all clocks even if a clock
operation fails. Do not propagate the errors so that the disable path
can perform as much cleanup as possible.
Fixes: 7384ecab34eb ("ASoC: mediatek: mt8196: support audio clock control")
Signed-off-by: bui duc phuc <phucduc.bui@gmail.com>
---
sound/soc/mediatek/mt8196/mt8196-afe-clk.c | 56 +++++++++++++---------
1 file changed, 34 insertions(+), 22 deletions(-)
diff --git a/sound/soc/mediatek/mt8196/mt8196-afe-clk.c b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
index 286e39f53ae0..91ae44024949 100644
--- a/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
+++ b/sound/soc/mediatek/mt8196/mt8196-afe-clk.c
@@ -220,33 +220,39 @@ static int apll1_mux_setting(struct mtk_base_afe *afe, bool enable)
ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1],
MT8196_AUD_ENG1_CLK);
if (ret)
- return ret;
+ goto err_disable_eng1;
ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
if (ret)
- return ret;
+ goto err_restore_eng1;
ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
apll_rate);
if (ret)
- return ret;
+ goto err_disable_audio_h;
} else {
- ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1],
- MT8196_AFE_26M);
- if (ret)
- return ret;
+ mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1],
+ MT8196_AFE_26M);
mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1]);
- ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
- MT8196_AFE_26M);
- if (ret)
- return ret;
+ mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
+ MT8196_AFE_26M);
mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
}
return 0;
+
+err_disable_audio_h:
+ mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+err_restore_eng1:
+ mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1],
+ MT8196_AFE_26M);
+err_disable_eng1:
+ mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG1]);
+
+ return ret;
}
static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
@@ -268,33 +274,39 @@ static int apll2_mux_setting(struct mtk_base_afe *afe, bool enable)
ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2],
MT8196_AUD_ENG2_CLK);
if (ret)
- return ret;
+ goto err_disable_eng2;
ret = mt8196_afe_enable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
if (ret)
- return ret;
+ goto err_restore_eng2;
ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
apll_rate);
if (ret)
- return ret;
+ goto err_disable_audio_h;
} else {
- ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2],
- MT8196_AFE_26M);
- if (ret)
- return ret;
+ mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2],
+ MT8196_AFE_26M);
mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2]);
- ret = mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
- MT8196_AFE_26M);
- if (ret)
- return ret;
+ mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H],
+ MT8196_AFE_26M);
mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
}
return 0;
+
+err_disable_audio_h:
+ mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUDIO_H]);
+err_restore_eng2:
+ mt8196_afe_set_clk_rate(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2],
+ MT8196_AFE_26M);
+err_disable_eng2:
+ mt8196_afe_disable_clk(afe, afe_priv->clk[MT8196_CLK_VLP_MUX_AUD_ENG2]);
+
+ return ret;
}
int mt8196_apll1_enable(struct mtk_base_afe *afe)
--
2.43.0
next prev parent reply other threads:[~2026-09-29 6:11 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-29 6:11 [PATCH 00/10] ASoC: mediatek: mt8196: Fix clock " phucduc.bui
2026-09-29 6:11 ` phucduc.bui [this message]
2026-09-29 6:11 ` [PATCH 02/10] ASoC: mediatek: mt8196: fix APLL enable " phucduc.bui
2026-09-29 6:11 ` [PATCH 03/10] ASoC: mediatek: mt8196: fix MCK " phucduc.bui
2026-09-29 6:11 ` [PATCH 04/10] ASoC: mediatek: mt8196: fix register access clock " phucduc.bui
2026-09-29 6:11 ` [PATCH 05/10] ASoC: mediatek: mt8196: propagate main clock errors phucduc.bui
2026-09-29 6:11 ` [PATCH 06/10] ASoC: mediatek: mt8196: use dev_err_probe() in mt8196_init_clock() phucduc.bui
2026-09-29 6:11 ` [PATCH 07/10] ASoC: mediatek: mt8196: fix runtime resume error handling phucduc.bui
2026-09-29 6:11 ` [PATCH 08/10] ASoC: mediatek: mt8196: remove redundant error message phucduc.bui
2026-09-29 6:11 ` [PATCH 09/10] ASoC: mediatek: mt8196: propagate I2S clock errors phucduc.bui
2026-09-29 6:11 ` [PATCH 10/10] ASoC: mediatek: mt8196: propagate TDM " phucduc.bui
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