From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 22C46417377; Tue, 29 Sep 2026 06:25:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790663135; cv=none; b=PjDIz6TxauQ9POQX96i88r1GF3dK0uXd7pOqNvg5qxy07Jqii1D1oD8KivoFw7PT6XGVdxw/Rwy2BOZp0v3WQFJQvUXkad6pVbae+cB61Un/JSMd6a8XEXx0zQl6kdxdggOUM5Ku7Oa6y1eaj0DzYYB6Cu8elvDSIfWXayIka4g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790663135; c=relaxed/simple; bh=UH4PiSFu3mxqAYITinPjSFO4MoWq3aSgekDOc9IDIXc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=gYjjoYAcBQRcI99X/UxA7Y9DJcSKaLV+j+w4sMQw6Xt9BI1PkMOuo5Q3qX10en4UkO2v7OWI/OzwkPx+cNkAx7T6L/jXzrUOYgfbYsX0/gCPhVwuOB45ubBLHl1AV+jB57QRb9MIDYv6+7aveyp9kfRKaAeLJN/PD6KOESZE6qs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=sv98azqC; arc=none smtp.client-ip=60.244.123.138 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="sv98azqC" X-UUID: 8be2bf5ebbce11f1b1788b6acf885367-20260929 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=QFc2KSUFkKfmphddM59adQNexTXZELrN5Dok5gsfyrE=; b=sv98azqCqgTtv2KffKwlQVQrS0/j1zkNyxTDSRBggjbhm7gtGsKBungqpegQPForoNy55vu+dIxIKVq1GrdnpyEcpuwHrpew9M0Ifa6jrcVCFHrz8x1chXf+GX8oVSgkNQLDvveei4y1kpXJ3WcoB36Rp/nJYqcP4oeyS5wCGyk=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.3.20,REQID:2adce123-1a01-449b-b65b-6079898aff43,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTIO N:release,TS:-25 X-CID-META: VersionHash:291e20b,CLOUDID:78fa25b6-eed8-408f-842a-a1c72425c9a0,B ulkID:nil,BulkQuantity:0,SF:81|82|102|136|836|865|888|898,TC:-5,Content:0| 15|50|99,EDM:-3|-100,IP:nil,URL:0,File:130,RT:0,Bulk:nil,QS:nil,BEC:-1,COL :0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 2,SSN|SDN X-CID-BAS: 2,SSN|SDN,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-CID-RHF: D41D8CD98F00B204E9800998ECF8427E X-UUID: 8be2bf5ebbce11f1b1788b6acf885367-20260929 Received: from mtkmbs13n1.mediatek.inc [(172.21.101.193)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 347195344; Tue, 29 Sep 2026 14:25:20 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.29; Tue, 29 Sep 2026 14:25:19 +0800 Received: from mtksitap99.mediatek.inc (10.233.130.16) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.2562.29 via Frontend Transport; Tue, 29 Sep 2026 14:25:19 +0800 From: Tim Kuo To: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno CC: , , , , , Steven Liu , Sky Huang , Tim Kuo Subject: [PATCH v2 2/2] spi: mt65xx: support wider tick delay field on IPM v59 Date: Tue, 29 Sep 2026 14:25:16 +0800 Message-ID: <20260929062516.416368-2-Tim.Kuo@mediatek.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20260929062516.416368-1-Tim.Kuo@mediatek.com> References: <20260929062516.416368-1-Tim.Kuo@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-MTK: N The IPM v59 SPI IP widens the tick delay field in SPI_CMD_REG from 3 bits (bits 24:22) to 7 bits (bits 28:22), so the field width can no longer be hardcoded in mtk_spi_hw_init(). Add a tick_dly_mask member to struct mtk_spi_compatible and use field_prep() with the per-SoC mask instead of the open-coded mask-and-shift, then add a mtk_ipm_v59_compat entry carrying the wider mask along with a "mediatek,spi-ipm-v59" compatible. Any further changes related to IPM v59 can be modified based on this compatible. Existing IPM designs keep GENMASK(24, 22) and are functionally unchanged. Signed-off-by: Tim Kuo --- v2: remove unused tickdly offset deadcode drivers/spi/spi-mt65xx.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-mt65xx.c b/drivers/spi/spi-mt65xx.c index b845a599f7c6..e9ec58ce1e1f 100644 --- a/drivers/spi/spi-mt65xx.c +++ b/drivers/spi/spi-mt65xx.c @@ -4,6 +4,7 @@ * Author: Leilk Liu */ +#include #include #include #include @@ -78,9 +79,9 @@ #define SPI_CMD_PAUSE_IE BIT(17) #define SPI_CMD_IPM_NONIDLE_MODE BIT(19) #define SPI_CMD_IPM_SPIM_LOOP BIT(21) -#define SPI_CMD_IPM_GET_TICKDLY_OFFSET 22 #define SPI_CMD_IPM_GET_TICKDLY_MASK GENMASK(24, 22) +#define SPI_CMD_IPM_V59_GET_TICKDLY_MASK GENMASK(28, 22) #define PIN_MODE_CFG(x) ((x) / 2) @@ -120,6 +121,7 @@ * @dma_ext: DMA address extension supported * @no_need_unprepare: Don't unprepare the SPI clk during runtime * @ipm_design: Adjust/extend registers to support IPM design IP features + * @tick_dly_mask: Tick delay field of SPI_CMD_REG, IPM designs only */ struct mtk_spi_compatible { bool need_pad_sel; @@ -128,6 +130,7 @@ struct mtk_spi_compatible { bool dma_ext; bool no_need_unprepare; bool ipm_design; + u32 tick_dly_mask; }; /** @@ -187,6 +190,15 @@ static const struct mtk_spi_compatible mtk_ipm_compat = { .enhance_timing = true, .dma_ext = true, .ipm_design = true, + .tick_dly_mask = SPI_CMD_IPM_GET_TICKDLY_MASK, +}; + +/* Every SoC with IPM v59 or newer shares this */ +static const struct mtk_spi_compatible mtk_ipm_v59_compat = { + .enhance_timing = true, + .dma_ext = true, + .ipm_design = true, + .tick_dly_mask = SPI_CMD_IPM_V59_GET_TICKDLY_MASK, }; static const struct mtk_spi_compatible mt6765_compat = { @@ -226,6 +238,7 @@ static const struct mtk_spi_compatible mt6991_compat = { .enhance_timing = true, .dma_ext = true, .ipm_design = true, + .tick_dly_mask = SPI_CMD_IPM_GET_TICKDLY_MASK, }; /* @@ -241,6 +254,9 @@ static const struct of_device_id mtk_spi_of_match[] = { { .compatible = "mediatek,spi-ipm", .data = (void *)&mtk_ipm_compat, }, + { .compatible = "mediatek,spi-ipm-v59", + .data = (void *)&mtk_ipm_v59_compat, + }, { .compatible = "mediatek,mt2701-spi", .data = (void *)&mtk_common_compat, }, @@ -366,7 +382,7 @@ static int mtk_spi_hw_init(struct spi_controller *host, struct spi_device *spi) { u16 cpha, cpol; - u32 reg_val; + u32 reg_val, mask; struct mtk_chip_config *chip_config = spi->controller_data; struct mtk_spi *mdata = spi_controller_get_devdata(host); @@ -443,10 +459,10 @@ static int mtk_spi_hw_init(struct spi_controller *host, /* tick delay */ if (mdata->dev_comp->enhance_timing) { if (mdata->dev_comp->ipm_design) { + mask = mdata->dev_comp->tick_dly_mask; reg_val = readl(mdata->base + SPI_CMD_REG); - reg_val &= ~SPI_CMD_IPM_GET_TICKDLY_MASK; - reg_val |= ((chip_config->tick_delay & 0x7) - << SPI_CMD_IPM_GET_TICKDLY_OFFSET); + reg_val &= ~mask; + reg_val |= field_prep(mask, chip_config->tick_delay); writel(reg_val, mdata->base + SPI_CMD_REG); } else { reg_val = readl(mdata->base + SPI_CFG1_REG); -- 2.45.2