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From: Petko Manolov <petko.manolov@konsulko.com>
To: Dinh Nguyen <dinguyen@kernel.org>
Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
	robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
	arnemaximilian.richter@draeger.com,
	martynas.grybauskas@draeger.com
Subject: Re: [PATCH v7 3/3] arm: dts: altera: add Draeger M48 CPU Module
Date: Tue, 29 Sep 2026 16:38:44 +0300	[thread overview]
Message-ID: <20260929133844.GF10296@carbon.k.g> (raw)
In-Reply-To: <ff085338-6310-42ac-8023-bdf6d48ad103@kernel.org>

On 26-09-28 09:18:03, Dinh Nguyen wrote:
> 
> According to all my documentations, the Cyclone5 SoCFPGA has 3 GPIO ports, and
> those are already mapped in the DTSI. The address space that you have
> specified here is for FPGA bridge. Which leads me to believe that this GPIO is
> in the FPGA.

You are correct.  These bindigs are some sort of leftover and Draeger folks
confirmed that they should be removed.

Sending out new patch series...


		Petko

      reply	other threads:[~2026-09-29 13:38 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-21  9:07 [PATCH v7 0/3] arm: dts: altera: add Draeger M48 CPU board Petko Manolov
2026-09-21  9:07 ` [PATCH v7 1/3] dt-bindings: vendor-prefixes: add Draeger AG Petko Manolov
2026-09-21  9:07 ` [PATCH v7 2/3] dt-bindings: arm: altera: add Draeger M48 dual-cpu board Petko Manolov
2026-09-28  5:53   ` Krzysztof Kozlowski
2026-09-21  9:07 ` [PATCH v7 3/3] arm: dts: altera: add Draeger M48 CPU Module Petko Manolov
2026-09-28 14:18   ` Dinh Nguyen
2026-09-29 13:38     ` Petko Manolov [this message]

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