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Tue, 29 Sep 2026 12:44:49 -0700 (PDT) Received: from localhost.localdomain ([82.142.85.166]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a014895428sm5265825e9.0.2026.09.29.12.44.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 29 Sep 2026 12:44:48 -0700 (PDT) From: Ginger Li To: Markus.Elfring@web.de, dmaengine@vger.kernel.org, linux-tegra@vger.kernel.org Cc: linux-kernel@vger.kernel.org, jonathanh@nvidia.com, ldewangan@nvidia.com, vkoul@kernel.org Subject: [PATCH v2] dmaengine: tegra186-gpc-dma: Read channel state under the lock Date: Tue, 29 Sep 2026 21:44:34 +0200 Message-ID: <20260929194434.29937-1-ginger.jzllee@gmail.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20260922072233.19592-1-ginger.jzllee@gmail.com> References: <20260922072233.19592-1-ginger.jzllee@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit tegra_dma_tx_status() reads tdc->status before taking tdc->vc.lock, and tegra_dma_isr() snapshots tdc->dma_desc before taking the same lock. All writers of these fields (tegra_dma_start(), tegra_dma_xfer_complete(), tegra_dma_pause(), tegra_dma_resume() and tegra_dma_terminate_all()) update them under tdc->vc.lock. The unlocked read in tegra_dma_tx_status() can therefore report DMA_PAUSED for a transfer that has already completed, and the unlocked read in tegra_dma_isr() can pick up a tdc->dma_desc which is being cleared concurrently, in which case the handler keeps using a stale descriptor pointer. Read both fields while holding tdc->vc.lock. Fixes: ee17028009d4 ("dmaengine: tegra: Add tegra gpcdma driver") Signed-off-by: Ginger Li --- v2: - Fixes: expanded to 12 hex digits. --- drivers/dma/tegra186-gpc-dma.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c --- a/drivers/dma/tegra186-gpc-dma.c +++ b/drivers/dma/tegra186-gpc-dma.c @@ -606,7 +606,7 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_id static irqreturn_t tegra_dma_isr(int irq, void *dev_id) { struct tegra_dma_channel *tdc = dev_id; - struct tegra_dma_desc *dma_desc = tdc->dma_desc; + struct tegra_dma_desc *dma_desc; struct tegra_dma_sg_req *sg_req; u32 status; @@ -619,6 +619,7 @@ static irqreturn_t tegra_dma_isr(int irq, void *dev_id } spin_lock(&tdc->vc.lock); + dma_desc = tdc->dma_desc; status = tdc_read(tdc, tdc->regs->status); if (!(status & TEGRA_GPCDMA_STATUS_ISE_EOC)) goto irq_done; @@ -786,10 +787,10 @@ static enum dma_status tegra_dma_tx_status(struct dma_ if (ret == DMA_COMPLETE) return ret; + spin_lock_irqsave(&tdc->vc.lock, flags); if (tdc->status == DMA_PAUSED) ret = DMA_PAUSED; - spin_lock_irqsave(&tdc->vc.lock, flags); vd = vchan_find_desc(&tdc->vc, cookie); if (vd) { dma_desc = vd_to_tegra_dma_desc(vd); -- 2.43.0