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On A306 a piglit tex-miplevel-selection run is a single submit of about 58k draws that takes 1.2-1.3 s to complete, and it gets reset partway through on every run. With the hangcheck period raised to 10 s the same runs pass without a hang. Compare the CP IB1/IB2 base and remaining size between timer expirations, like a6xx does. On A306 these move on every 20 ms sample while such a submit executes and read zero when idle. The prefetch queues are small (32 and 64 for IB1 and IB2), so buffered data does not hide progress for long. Assisted-by: LLM Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 0259e60b8011..c95bbb4bcf47 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -536,6 +536,23 @@ static u32 a3xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return ring->memptrs->rptr; } +static bool a3xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) +{ + struct msm_cp_state cp_state = { + .ib1_base = gpu_read(gpu, REG_AXXX_CP_IB1_BASE), + .ib2_base = gpu_read(gpu, REG_AXXX_CP_IB2_BASE), + .ib1_rem = gpu_read(gpu, REG_AXXX_CP_IB1_BUFSZ), + .ib2_rem = gpu_read(gpu, REG_AXXX_CP_IB2_BUFSZ), + }; + bool progress; + + progress = !!memcmp(&cp_state, &ring->last_cp_state, sizeof(cp_state)); + + ring->last_cp_state = cp_state; + + return progress; +} + static struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) { struct a3xx_gpu *a3xx_gpu = NULL; @@ -630,6 +647,7 @@ const struct adreno_gpu_funcs a3xx_gpu_funcs = { .gpu_state_put = adreno_gpu_state_put, .create_vm = adreno_create_vm, .get_rptr = a3xx_get_rptr, + .progress = a3xx_progress, }, .init = a3xx_gpu_init, }; -- 2.47.3