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Tue, 29 Sep 2026 22:32:57 -0500 From: David Zhang To: , , , , , , CC: David Zhang , , Subject: [PATCH V1 10/20] accel/amdxdna: Refactor AIE4 hardware initialization sequence Date: Tue, 29 Sep 2026 20:32:23 -0700 Message-ID: <20260930033233.1727265-11-yidong.zhang@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260930033233.1727265-1-yidong.zhang@amd.com> References: <20260930033233.1727265-1-yidong.zhang@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00002323:EE_|PH8PR12MB7422:EE_ X-MS-Office365-Filtering-Correlation-Id: 92185e2f-7a09-41b5-e93e-08df1ea388d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|1800799024|376014|82310400026|10067099003|4143699003|56012099006|3023799007|6133799003|11063799006|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: oH+1etiRB3FVrxiUjVB+FHW+jPyN0hBg2Oh+BnLSm/CTmYaOBZfN7yvHkHp/HBXweLLm/IixYJ2UCMuzNDaabIe8tBHuBnUYDBPlpMWXNcVKOz29vTt5XAa3MSZEBxt4QF40cbocQwURUT6v72DgNk/bgoKX3Tk0fG3eOOBgwhGaP64ELhOXcpjmPcgoZv+8chVdhR8xZXk3g+Cg7/6n2HG29PdubTq8d08AFSSVz634hUA5fVogyPWuttmX/Dc8Y04f8rDhp4htopepNRkq/OwBLasL2LUV7zG6zevyWvhMxaQgA+NHJYG0Yi2w3kuIB5mb5ghfn/DNnH6OiPbcZIAa1DvrCUOoarHabWCI/6N0vGWyEfV9nyK9pDX15vZysgPiqrkbw3g5bemZ2UZLsmFN34C9P4bmuMKQcVTuDmZ1MvTSSr8GieQEc/idn42Q X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 03:33:03.3119 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92185e2f-7a09-41b5-e93e-08df1ea388d5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00002323.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7422 Reorganize AIE4 hardware initialization into distinct phases: - aie4_query_fw(): Query NPU and CERT firmware versions. - aie4_config_fw(): Attach work buffer and configure context switch hysteresis. - aie4_setup_aie(): Query AIE version, metadata, initialize DPM frequency table, and initialize partitions. Update aie4_pf_hw_start(), aie4_vf_hw_start(), and aie4_classic_hw_start() to use these phases and unify error unwinding labels. As part of this, aie4_pf_hw_start() now also calls aie4_query_fw(), which it previously did not do. Additionally: - Zero-initialize struct smu_config smu_conf in aie4_prepare_firmware(). - Clean up iomem pointer type in aie4_fw_is_alive() to void __iomem *. Signed-off-by: David Zhang --- drivers/accel/amdxdna/aie4_pci.c | 82 +++++++++++++++++++------------- 1 file changed, 50 insertions(+), 32 deletions(-) diff --git a/drivers/accel/amdxdna/aie4_pci.c b/drivers/accel/amdxdna/aie4_pci.c index 60348ec5bc53..b1742116bedd 100644 --- a/drivers/accel/amdxdna/aie4_pci.c +++ b/drivers/accel/amdxdna/aie4_pci.c @@ -49,7 +49,7 @@ static int aie4_fw_is_alive(struct amdxdna_dev *xdna) { const struct amdxdna_dev_priv *npriv = xdna->dev_info->dev_priv; struct amdxdna_dev_hdl *ndev = xdna->dev_handle; - u32 __iomem *src; + void __iomem *src; u32 fw_is_valid; int ret; @@ -273,7 +273,13 @@ static void aie4_partition_fini(struct amdxdna_dev_hdl *ndev) XDNA_ERR(xdna, "partition fini failed: %d", ret); } -static int aie4_query(struct amdxdna_dev_hdl *ndev) +/* + * Called by all three hw_start paths (PF, VF, classic) right after mailbox + * init. aie4_query_cert_firmware_version() runs a CERT protocol + * compatibility check, so firmware/driver compatibility is intentionally + * verified before any other firmware operation is attempted. + */ +static int aie4_query_fw(struct amdxdna_dev_hdl *ndev) { struct amdxdna_dev *xdna = ndev->aie.xdna; int ret; @@ -286,23 +292,6 @@ static int aie4_query(struct amdxdna_dev_hdl *ndev) if (ret) return ret; - ret = aie4_query_aie_version(ndev, &ndev->aie.version); - if (ret) - return ret; - - ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata); - if (ret) - return ret; - - ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols); - - ret = aie4_init_dpm_freq_table(ndev); - if (ret) { - /* if query dpm from fw failed, using default value */ - if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm) - (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0); - } - return 0; } @@ -341,6 +330,30 @@ static int aie4_config_fw(struct amdxdna_dev_hdl *ndev) return 0; } +static int aie4_setup_aie(struct amdxdna_dev_hdl *ndev) +{ + int ret; + + ret = aie4_query_aie_version(ndev, &ndev->aie.version); + if (ret) + return ret; + + ret = aie4_query_aie_metadata(ndev, &ndev->aie.metadata); + if (ret) + return ret; + + ndev->total_col = min_t(u32, AIE4_TOTAL_COLUMN, ndev->aie.metadata.cols); + + ret = aie4_init_dpm_freq_table(ndev); + if (ret) { + /* if query dpm from fw failed, using default value */ + if (ndev->priv->hw_ops && ndev->priv->hw_ops->set_dpm) + (void)ndev->priv->hw_ops->set_dpm(&ndev->aie, 0); + } + + return aie4_partition_init(ndev); +} + static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev) { int ret; @@ -353,6 +366,10 @@ static int aie4_pf_hw_start(struct amdxdna_dev_hdl *ndev) if (ret) goto stop_fw; + ret = aie4_query_fw(ndev); + if (ret) + goto mbox_fini; + ret = aie4_config_fw(ndev); if (ret) goto mbox_fini; @@ -390,21 +407,21 @@ static int aie4_vf_hw_start(struct amdxdna_dev_hdl *ndev) if (ret) return ret; - ret = aie4_query(ndev); + ret = aie4_query_fw(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; - ret = aie4_partition_init(ndev); + ret = aie4_setup_aie(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; ret = aie4_restore_power_mode(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; return 0; -mailbox_fini: +mbox_fini: aie4_mailbox_fini(ndev); return ret; } @@ -431,17 +448,17 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev) if (ret) goto stop_fw; - ret = aie4_query(ndev); + ret = aie4_query_fw(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; ret = aie4_config_fw(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; - ret = aie4_partition_init(ndev); + ret = aie4_setup_aie(ndev); if (ret) - goto mailbox_fini; + goto mbox_fini; ret = aie4_restore_power_mode(ndev); if (ret) @@ -451,10 +468,11 @@ static int aie4_classic_hw_start(struct amdxdna_dev_hdl *ndev) partition_fini: aie4_partition_fini(ndev); -mailbox_fini: +mbox_fini: aie4_mailbox_fini(ndev); stop_fw: aie4_fw_stop(ndev); + return ret; } @@ -528,8 +546,8 @@ static int aie4_prepare_firmware(struct amdxdna_dev_hdl *ndev, void __iomem *tbl[PCI_NUM_RESOURCES]) { struct amdxdna_dev *xdna = ndev->aie.xdna; + struct smu_config smu_conf = {}; struct psp_config psp_conf; - struct smu_config smu_conf; int i; psp_conf.fw_size = npufw->size; -- 2.34.1