[PATCH v5 05/15] gpu: nova-core: add the per-architecture GIN CPU interrupt HAL

[John Hubbard <jhubbard@nvidia.com>]

The GIN CPU interrupt tree differs by GPU family in two ways:

* The size of the tree. Turing, Ampere and Ada implement 8 leaves.
  Hopper and later families implement 16.

* The write that rearms delivery. A message-signaled interrupt is
  delivered once per edge, and the PCI side delivers nothing more until
  the CPU rearms it. Before Hopper, MSI rearms by writing the
  end-of-interrupt register in the BAR0 mirror of PCI configuration
  space. On Hopper and later, MSI rearms by clearing and then setting
  the TOP enables of every serviced subtree, which produces a new edge.
  MSI-X rearms the same way on every family, but for the handler's own
  subtree only, since each subtree has its own table entry.

Add an interrupt HAL that provides the leaf count and performs the rearm
for each family. Name the interrupt type with two variants, MSI and
MSI-X, since nova-core never allocates the level-triggered INTx that the
kernel's PCI interrupt type also names.

The HAL has no user yet.

Assisted-by: LLM
Reviewed-by: Will Pierce <wpierce@nvidia.com>
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
---
 drivers/gpu/nova-core/irq.rs           | 13 +++++
 drivers/gpu/nova-core/irq/hal.rs       | 67 ++++++++++++++++++++++++++
 drivers/gpu/nova-core/irq/hal/gh100.rs | 40 +++++++++++++++
 drivers/gpu/nova-core/irq/hal/tu102.rs | 43 +++++++++++++++++
 4 files changed, 163 insertions(+)
 create mode 100644 drivers/gpu/nova-core/irq/hal.rs
 create mode 100644 drivers/gpu/nova-core/irq/hal/gh100.rs
 create mode 100644 drivers/gpu/nova-core/irq/hal/tu102.rs

diff --git a/drivers/gpu/nova-core/irq.rs b/drivers/gpu/nova-core/irq.rs
index 1ec0bb055d3b..62c242b71dc8 100644
--- a/drivers/gpu/nova-core/irq.rs
+++ b/drivers/gpu/nova-core/irq.rs
@@ -9,5 +9,18 @@
 //!
 //! See `Documentation/gpu/nova/core/interrupts.rst`.
 
+mod hal;
 mod interrupt_tree;
 mod regs;
+
+/// The message-signaled interrupt type that Linux granted.
+///
+/// nova-core never requests INTx, so this has no variant for it, unlike [`kernel::pci::IrqType`].
+#[derive(Clone, Copy, Debug, Eq, PartialEq)]
+enum MsiType {
+    /// A single message, which every subtree raises.
+    Msi,
+
+    /// One table entry per subtree.
+    MsiX,
+}
diff --git a/drivers/gpu/nova-core/irq/hal.rs b/drivers/gpu/nova-core/irq/hal.rs
new file mode 100644
index 000000000000..387695cca37b
--- /dev/null
+++ b/drivers/gpu/nova-core/irq/hal.rs
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+//! Per-architecture differences in the GIN CPU interrupt tree.
+//!
+//! See "Per-architecture differences" in `Documentation/gpu/nova/core/interrupts.rst`.
+
+mod gh100;
+mod tu102;
+
+use kernel::{
+    io::Io,
+    prelude::*, //
+};
+
+use crate::{
+    driver::Bar0,
+    gpu::{
+        Architecture,
+        Chipset, //
+    }, //
+};
+
+use super::{
+    interrupt_tree::{
+        LeafCount,
+        Subtree,
+        SubtreeSet, //
+    },
+    regs::*,
+    MsiType, //
+};
+
+/// Clears and then sets the `TOP` enables of `subtrees`, which produces a new delivery edge.
+fn cycle_top_enables(bar: Bar0<'_>, subtrees: SubtreeSet) {
+    bar.write_reg(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_CLEAR::zeroed().with_subtrees(subtrees));
+    bar.write_reg(NV_VIRTUAL_FUNCTION_PRIV_CPU_INTR_TOP_EN_SET::zeroed().with_subtrees(subtrees));
+}
+
+/// The leaf count and the rearm of the GIN CPU tree, which differ by GPU family.
+pub(super) trait CpuInterruptHal: Send + Sync {
+    /// Returns the number of leaves the tree implements.
+    fn leaf_count(&self) -> LeafCount;
+
+    /// Rearms PCI interrupt delivery after a handler serviced `subtree`.
+    ///
+    /// `serviced` is every subtree that nova-core services, for the Hopper-plus MSI form, which
+    /// cycles the `TOP` enables of them all. See "Rearming PCI interrupt delivery" in
+    /// `Documentation/gpu/nova/core/interrupts.rst`.
+    fn rearm_pci_irq(
+        &self,
+        bar: Bar0<'_>,
+        msi_type: MsiType,
+        serviced: SubtreeSet,
+        subtree: Subtree,
+    );
+}
+
+/// Returns the [`CpuInterruptHal`] for `chipset`'s architecture.
+pub(super) fn cpu_interrupt_hal(chipset: Chipset) -> &'static dyn CpuInterruptHal {
+    match chipset.arch() {
+        Architecture::Turing | Architecture::Ampere | Architecture::Ada => tu102::TU102_HAL,
+        Architecture::Hopper | Architecture::BlackwellGB10x | Architecture::BlackwellGB20x => {
+            gh100::GH100_HAL
+        }
+    }
+}
diff --git a/drivers/gpu/nova-core/irq/hal/gh100.rs b/drivers/gpu/nova-core/irq/hal/gh100.rs
new file mode 100644
index 000000000000..6e307c8d120b
--- /dev/null
+++ b/drivers/gpu/nova-core/irq/hal/gh100.rs
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+use crate::driver::Bar0;
+
+use super::{
+    cycle_top_enables,
+    CpuInterruptHal,
+    LeafCount,
+    MsiType,
+    Subtree,
+    SubtreeSet, //
+};
+
+/// The CPU interrupt tree properties of Hopper and Blackwell.
+struct Gh100;
+
+impl CpuInterruptHal for Gh100 {
+    fn leaf_count(&self) -> LeafCount {
+        LeafCount::Sixteen
+    }
+
+    fn rearm_pci_irq(
+        &self,
+        bar: Bar0<'_>,
+        msi_type: MsiType,
+        serviced: SubtreeSet,
+        subtree: Subtree,
+    ) {
+        let subtrees = match msi_type {
+            MsiType::Msi => serviced,
+            MsiType::MsiX => subtree.into(),
+        };
+
+        cycle_top_enables(bar, subtrees);
+    }
+}
+
+const GH100: Gh100 = Gh100;
+pub(super) const GH100_HAL: &dyn CpuInterruptHal = &GH100;
diff --git a/drivers/gpu/nova-core/irq/hal/tu102.rs b/drivers/gpu/nova-core/irq/hal/tu102.rs
new file mode 100644
index 000000000000..7e3aea946d05
--- /dev/null
+++ b/drivers/gpu/nova-core/irq/hal/tu102.rs
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: GPL-2.0
+// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+
+use kernel::io::Io;
+
+use crate::{
+    driver::Bar0,
+    irq::regs::NV_XVE_CYA_2, //
+};
+
+use super::{
+    cycle_top_enables,
+    CpuInterruptHal,
+    LeafCount,
+    MsiType,
+    Subtree,
+    SubtreeSet, //
+};
+
+/// The CPU interrupt tree properties of Turing, Ampere, and Ada.
+struct Tu102;
+
+impl CpuInterruptHal for Tu102 {
+    fn leaf_count(&self) -> LeafCount {
+        LeafCount::Eight
+    }
+
+    fn rearm_pci_irq(
+        &self,
+        bar: Bar0<'_>,
+        msi_type: MsiType,
+        _serviced: SubtreeSet,
+        subtree: Subtree,
+    ) {
+        match msi_type {
+            MsiType::Msi => bar.write(NV_XVE_CYA_2, 0u32.into()),
+            MsiType::MsiX => cycle_top_enables(bar, subtree.into()),
+        }
+    }
+}
+
+const TU102: Tu102 = Tu102;
+pub(super) const TU102_HAL: &dyn CpuInterruptHal = &TU102;
-- 
2.55.0