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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?J/9OEBxMdRezBptSYpKkVCUK38PQwS4RoKGc2hUlR6SJ6IGBdYm9HZK7k/9P?= =?us-ascii?Q?NfJykNt13AT70xN0rSqSWK/nOMZvFXQgxxCcYJRFdYRNgXB1kN8HvhDhW1Ab?= =?us-ascii?Q?VhuByOKc56BDCp06rVb00OX5TcEnQt2WlY6AQxFm5IXJ87XzkUSIWBOZ/1T6?= =?us-ascii?Q?cwR2epi5TPbEp7zCrJedYaN9oFAQ1wQxfTzx9I1TozklDU/XLNI/k/y0B159?= =?us-ascii?Q?ud5hjAtQBKe6goBE3eXANPHtyuXVDmqVTeBf4N/HfPgRfB3q31AzObVqYNt7?= =?us-ascii?Q?bsuBfD/360Swpvkxfl9tg5FI+Kx+uA44UhA/mX4QXwXpAPNt2z5+1GoFrpZg?= =?us-ascii?Q?AonlF54Hc4zDPBzaOxuyODOxNXR/SvwaCnZqCySn4zl8vWnw2jK/82iyToIG?= =?us-ascii?Q?lX7NylmNnXPzYiEXT1/OxyMQ9U6S99ESzosI6K6vml2Nl0P4gWvPOTRhLE2Q?= =?us-ascii?Q?3rdUq9WWWk5uoY6BndtxK601mJEeOYb9+Zh2Rk+xDCoRFZxxB14Kw0eHlXjF?= =?us-ascii?Q?YbkFnp+wJWFUsSAPfPZA1nv4ipWMz9+oPb0SRIt4hmvMyqBxh+r8Ug5V+Gzt?= =?us-ascii?Q?waPL6/YL6NgnqJrFx3F/c8yUZDVxaZdd5rjfRN+i7fDDXykmSXAnqPq2oNQR?= =?us-ascii?Q?dDRXHXb/8/hZ+MD7Gbsvvhj96F04IMlsafCzJBI3deP9AC4sOJiOqtQIWjRY?= =?us-ascii?Q?Ex9skx2lkSB2OdnzgGK77ePvvKw7RQ1tmNrRakH5cbZBQDit79PzTiRkuLwI?= =?us-ascii?Q?hzaRO7c9rrbbpQzfduC+PO8CA4xufSO5bedq9CctI/ptBZdujPaiZBEw9Dza?= =?us-ascii?Q?UHTSy3YAjELDiBkCxOL4q6FsTCRFc0RsnzZHO+mip3/i8YQ98FOrUZZf4pym?= =?us-ascii?Q?XL8PFMfwAWOWq5WIjoo3jUzRFs+6DYbhRzzwNTkbyyKLmxoi/MiHnbqbC8LX?= =?us-ascii?Q?m3Iz56aOxraXMh+O0GlF8wj4QXKg9aO9Sf3E5XFhDBhOP6QubgyOv8mP8Q7O?= =?us-ascii?Q?p4cO3+Dh6/p4VMmQJ4wQam/A6feXFkfj9ahTcKUDbGpkPRb3AHQ+WgYCef3E?= =?us-ascii?Q?QVmzkpuADX1fbTMUouoYEEAvzMlyHzpWZi6fpCrCEfsqk7buQxI4OGv+SOdx?= =?us-ascii?Q?q8uTjc5Lmtf+8nX8o3rDITJfbI60pUTBLfZ6fwnQpUrIMZVsQW603qrJ6pRL?= =?us-ascii?Q?Qb/kxfI5JNYlgCzGUcfCX25w8NIttfg8i1yDFyFnZWQR0PBtTTSM1yOTjVm7?= =?us-ascii?Q?6wyzhi9RIr2rmO464Nm+NWqqVlj8lvBauWxxOoHL5Is9GO+oxVy1eBXiXo3Q?= =?us-ascii?Q?e9w9j5sYIuqvMaBplo03PWK+ydF49km8goiXACiUHlziH030A7KrFKNL7lxP?= =?us-ascii?Q?0XJ6wHrGWhoQcxEX8NkAQCLbRTBMs1dRqKtFKlNWXNm5a0tOZv+/SheOXvqq?= =?us-ascii?Q?Pxprjcd5Anlutlb/WVOxqHllobA9DVOJOc66f5xFZwgcbtn4SlnmePybva4R?= =?us-ascii?Q?NfDW5YkrnGteDBmMYTUS4bZPW59PwKYp9hfEWFM8hslX876YD39QhhDsliFk?= =?us-ascii?Q?pf59ZKqr6JUZ4Pp1UP3zUSbwcQDvgMd7WpHg0JcbuPnKiGkWZ9iU6RuLr6IL?= =?us-ascii?Q?RQ/f743y19278sy64dVI56p60LpQRwfwQp7oBsA3TIhoIWU+WqVebkzjc5e9?= =?us-ascii?Q?Xycxgj2fuIqawZQHSPCU+7rt3wMulabN2u6mZjy+SVnyfQh0BtCIOQzdoNEF?= =?us-ascii?Q?M3TjnrkSIw=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 86789135-a92a-4fbf-6720-08df1ea4d325 X-MS-Exchange-CrossTenant-AuthSource: DM3PR12MB9416.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 03:42:17.7147 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: GYbhLKO6Ha/1GCb5bG4dPK7S0XlWmH2yBKftHU+UdjF7iDrvrwUBq/Ld7BbxeBOuI7drOx8IqqLWWHQn/Itv6w== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6248 The GPU boots its own firmware, GFW, out of reset, and the driver must not program the GPU until GFW reports completion. nova-core waited for GFW inside the Gpu constructor, which also boots the GSP. Code that has to run after GFW and before GSP boot, such as a probe-time hardware self-test, had nowhere to go. Move the wait into probe, ahead of the Gpu constructor, and read the chipset there from a Spec that probe builds itself. Leave the DMA mask in the constructor, since it programs the host rather than the GPU. Assisted-by: LLM Signed-off-by: John Hubbard --- drivers/gpu/nova-core/driver.rs | 14 +++++++++++++- drivers/gpu/nova-core/gpu.rs | 26 +++++++++++++++++++------- 2 files changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driver.rs index 291a047e4d86..fc321c6a10b0 100644 --- a/drivers/gpu/nova-core/driver.rs +++ b/drivers/gpu/nova-core/driver.rs @@ -24,7 +24,11 @@ use crate::{ api::NovaCoreApi, - gpu::Gpu, // + gpu::{ + self, + Gpu, + Spec, // + }, // }; /// Counter for generating unique auxiliary device IDs. @@ -113,6 +117,14 @@ fn probe<'bound>( pdev.iomap_region(bar1_idx, c"nova-core/bar1")? }, + _: { + let spec = Spec::new(pdev.as_ref(), bar)?; + + // We must wait for GFW_BOOT completion before doing any significant setup on + // the GPU. + gpu::wait_gfw_boot_completion(pdev.as_ref(), bar, spec.chipset)?; + }, + // TODO: Use self-referential pin-init syntax once available. gpu <- Gpu::new( pdev, diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs index fb6f8a86a503..65715f906030 100644 --- a/drivers/gpu/nova-core/gpu.rs +++ b/drivers/gpu/nova-core/gpu.rs @@ -251,7 +251,7 @@ pub struct Spec { } impl Spec { - fn new(dev: &device::Device, bar: Bar0<'_>) -> Result { + pub(crate) fn new(dev: &device::Device, bar: Bar0<'_>) -> Result { // Some brief notes about boot0 and boot42, in chronological order: // // NV04 through NV50: @@ -397,10 +397,8 @@ pub(crate) fn new<'a>( dev_info!(dev,"NVIDIA ({})\n", spec); })?, - // We must wait for GFW_BOOT completion before doing any significant setup on the GPU. _: { - let hal = hal::gpu_hal(spec.chipset); - let dma_mask = hal.dma_mask(); + let dma_mask = hal::gpu_hal(spec.chipset).dma_mask(); // SAFETY: `Gpu` owns all DMA allocations for this device, and we are // still constructing it, so no concurrent DMA allocations can exist. @@ -412,9 +410,6 @@ pub(crate) fn new<'a>( // SAFETY: `Gpu` owns all DMA allocations for this device, and we are // still constructing it, so no concurrent DMA allocations can exist. unsafe { pdev.dma_set_max_seg_size(u32::MAX) }; - - hal.wait_gfw_boot_completion(bar) - .inspect_err(|_| dev_err!(dev, "GFW boot did not complete\n"))?; }, // Initialize this early because `gsp_resources` depends on it. @@ -533,6 +528,23 @@ pub(crate) fn run_selftests(self: Pin<&mut Self>, pdev: &pci::Device, + bar: Bar0<'_>, + chipset: Chipset, +) -> Result { + hal::gpu_hal(chipset) + .wait_gfw_boot_completion(bar) + .inspect_err(|_| dev_err!(dev, "GFW boot did not complete\n")) +} + /// Reads the boot0 register and returns its raw value. pub(crate) fn boot_0_raw(bar: Bar0<'_>) -> u32 { bar.read(regs::NV_PMC_BOOT_0).into_raw() -- 2.55.0