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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-14d08fb50f1sm2711531c88.13.2026.09.29.23.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Sep 2026 23:39:28 -0700 (PDT) From: Himanshu Chauhan To: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-perf-users@vger.kernel.org Cc: peterz@infradead.org, mingo@redhat.com, alex@ghiti.fr, aou@eecs.berkeley.edu, jtaubepe@redhat.com, palmer@dabbelt.com, pjw@kernel.org, qingfang.deng@linux.dev, shuah@kernel.org, thecharlesjenkins@gmail.com, cp0613@linux.alibaba.com, Himanshu Chauhan Subject: [PATCH v7 0/8] riscv: Introduce support for hardware break/watchpoints Date: Wed, 30 Sep 2026 12:09:11 +0530 Message-ID: <20260930063919.608911-1-himanshu.chauhan@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=cqgOAF4i c=1 sm=1 tr=0 ts=6abcaea3 cx=c_pps a=JYo30EpNSr/tUYqK9jHPoA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=V1jnuoLLAAAA:20 a=NEAV23lmAAAA:8 a=ClvrxCKNdzey32-IL00A:9 a=Fk4IpSoW4aLDllm1B1p-:22 a=bA3UWDv6hWIuX7UZL3qL:22 X-Proofpoint-GUID: 8lwI50h3wl0NaeE6RI-_1cEcRFR6P8SX X-Proofpoint-ORIG-GUID: 8lwI50h3wl0NaeE6RI-_1cEcRFR6P8SX X-Proofpoint-Spam-Info: AW1haW4tMjYwOTMwMDAyNiBTYWx0ZWRfX42sV7SZkC6zt e1SS3uxrqR2Njw8GLAHglUoUXtigB0vU4PFeztLahZAQ8eDTv1CdmFpXpk5BpJ9VwFEFaX8e8uU feMch4yJUThGLWl348Z94PIgJvLMJAw= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTMwMDAyNiBTYWx0ZWRfXwoJRNk+nK8xl iW8BuzsPueaNDxO3zbKQvF1ZusJ7iWC1cUEyAJZILHxERsCew1Dk/Q6fwv2vhAyqPGIbK7S35uO g4rsuq8471PQ2lou1KxMrsmw1fLhV04vqyB4UL2BNp4NJt6Ij0ql+FjN+ijHfYZGE8Mj3TFzZqA MfosaNnouCBvEy6jo/tgqqrAUE7TPm7LAMqNpnUAC5e2e4+tRwbRmIH1brmLwkd8lUszLDtEz1A OJhLpogg9O/Sp7Dc+fUJW74L+awrJ3Rs5TH9jF44B4mg97x1ZKVpRtn0n2pfItNQfkfbZTqwLHA T4+QyqmYazsXMOlPIPZTnI/7oAMCp/j7UaKMsTN99afsybr4NO6WqDdZktLiSMsCMliDUsUctOb sdtDu8eHXNbkdlIgx8vpYImA4k4ZBAe2vRfYFtd5UGX2B2FbnhUJ5OiJl6QXSY1zonmeDqdc1/M EH5Mcd76iL4R5CU6OTA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-29_05,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 adultscore=0 bulkscore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609300026 This patchset adds support for hardware breakpoints and watchpoints in the RISC-V architecture. The framework is built on top of the perf/ptrace subsystem and the SBI debug trigger extension (Sdtrig). Single stepping is ready with software support and mc6. Once, icount is fixed, the software supported single stepping will be put under a Kconfig option. Until then its default. Virtualization of debug triggers are pending. Patch set is ready but needs testing. Changes from v6: - Rebased to v7.3-rc5 - Added HIT0/1 bit check/clear in breakpoint handler with EPC/Bp address check - Removed dbtr_shmem null check as pointed by Qinfang Deng - Fixed MEM_HI/MEM_LO macros to work both on rv64/32 - Changed unsigned long to __u64 from hwdebug state struct and dropped packing - Gated HAVE_MIXED_BREAKPOINT_REGS with PERF_EVENTS - Software base single stepping with mcontrol6 trigger type. - icount is still under development. - Moved and and reworked instruction decoding code to a common file. - perf test suite now supported. - Breakpoint overflow signal handler - Breakpoint overflow sampling - Breakpoint accounting (needs sudo) - Watchpoint - Read Only Watchpoint - Write Only Watchpoint - Read / Write Watchpoint - Modify Watchpoint - __test_function in "Breakpoint overflow signal handler" is name noinline - Fixed warnings from checkpatch.pl --strict Changes from v5: - Rebased to v7.2-rc6 - Simplified Macros in hw_breakpoint.h - Took care of the review comments - Added ptrace support for hardware break/watchpoints (new patch) - PTRACE_GETREGSET/SETREGSET via NT_RISCV_HW_BREAK / NT_RISCV_HW_WATCH - PTRACE_GETHBPREGS / SETHBPREGS for direct single-trigger access - HAVE_MIXED_BREAKPOINTS_REGS selected (break/watch share trigger pool) - flush_ptrace_hw_breakpoint / ptrace_hw_copy_thread wired up - Extended selftest to cover ptrace-based hw break/watchpoint paths (new patch) Changes from v4: - Rebased to v7.2-rc4 - Fixed rv32 build error - Added pr_fmt to print KBUILD_MODNAME - Changed type of shmem_pa to phys_addr_t - Use per_cpu_ptr_to_phys instead of __pa for per-cpu allocated memory - Print successful registration/unregistration message when no error - Added RISC-V DEBUGGING section in MAINTAINERS and added myself as maintainer - Fixed warnings from checkpatch.pl --strict run Changes from v3: - Rebased to v7.1-rc3 - For watchpoints, check tdata1.hit via SBI_EXT_DBTR_TRIG_READ and keep STVAL-based matching as fallback - Improved watchpoint matching when STVAL reports the lowest accessed address for wider memory accesses - Program execute breakpoints with SIZE=0 (match any size) to avoid misses with 16-bit/compressed instruction addresses - Updated selftest to avoid deadlock by replacing unbounded sem_wait() with sem_timedwait() timeout handling - Updated selftest breakpoint function so it cannot be inlined or optimized away Changes from v2: - Rebased to v7.0-rc1 - Fixed warnings from checkpatch.pl --strict run Changes from v1: - The patch adding the SBI extension and function IDs is already merged; this series builds on top of that - Added breakpoint selftest in tools/testing/selftests/breakpoints/ Specifications: ~~~~~~~~~~~~~~ The SBI debug trigger extension is specified in Chapter 19 of the SBI specification: https://github.com/riscv-non-isa/riscv-sbi-doc/releases/download/v3.0/riscv-sbi.pdf The Sdtrig ISA is part of the RISC-V debug specification: https://github.com/riscv/riscv-debug-spec How to use: ~~~~~~~~~~~ OpenSBI: https://github.com/riscv-software-src/opensbi.git QEMU: https://github.com/qemu/qemu.git Linux Kernel: Apply these patches on top of v7.3-rc5 How to test: ~~~~~~~~~~~ >From the Linux kernel directory, first install the UAPI headers (required on a fresh tree so the compiler can locate and the new NT_RISCV_HW_BREAK/WATCH definitions via KHDR_INCLUDES): make headers Then build the selftest: make -C tools/testing/selftests/breakpoints/ This produces breakpoint_test_riscv under the same directory. Load it on the target and run. Sample output: # /apps/breakpoint_test_riscv # [perf_event]: Breakpoint test passed! # [perf_event]: Watchpoint test passed! # [ptrace]: Breakpoint test passed! # ptrace(PTRACE_GETREGSET): Number of watchpoints: 2 # ptrace(PTRACE_GETREGSet): addr: 0x82888 control: 0x8080 # [ptrace]: Watchpoint test passed! # [hbpregs] breakpoint readback: addr=0x10472 type=4 len=4 ctrl=0 # [hbpregs]: Breakpoint test passed! # [hbpregs] watchpoint readback: addr=0x82888 type=2 len=8 ctrl=0 # [hbpregs]: Watchpoint test passed! Perf Test Suite: ~~~~~~~~~~~~~~~ ~ # /apps/perf test -v 16 17 18 19 16: Breakpoint overflow signal handler : Ok 17: Breakpoint overflow sampling : Ok 18: Breakpoint accounting : Ok 19: Watchpoint : 19.1: Read Only Watchpoint : Ok 19.2: Write Only Watchpoint : Ok 19.3: Read / Write Watchpoint : Ok 19.4: Modify Watchpoint : Ok === Test Summary === Passed main tests : 3 Passed subtests : 4 Skipped tests : 0 Failed tests : 0 Himanshu Chauhan (8): riscv: Introduce support for hardware break/watchpoints riscv: Add breakpoint and watchpoint test for riscv riscv: ptrace support for hardware break/watchpoints selftests/breakpoints: extend riscv test for ptrace hw break/watchpoints RISC-V: Add fetch and decode helpers to a common file riscv: Add software supported single stepping with mc/mc6 triggers perf tests: add noinline to __test_function MAINTAINERS: Add entry for RISC-V Debugging MAINTAINERS | 11 + arch/riscv/Kconfig | 3 + arch/riscv/include/asm/hw_breakpoint.h | 331 +++++++ arch/riscv/include/asm/insn.h | 15 + arch/riscv/include/asm/kdebug.h | 3 +- arch/riscv/include/asm/processor.h | 18 + arch/riscv/include/uapi/asm/ptrace.h | 50 + arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/hw_breakpoint.c | 879 ++++++++++++++++++ arch/riscv/kernel/process.c | 5 + arch/riscv/kernel/ptrace.c | 507 ++++++++++ arch/riscv/kernel/traps.c | 6 + arch/riscv/kernel/traps_misaligned.c | 52 +- arch/riscv/lib/Makefile | 1 + arch/riscv/lib/insn.c | 263 ++++++ include/uapi/linux/elf.h | 4 + tools/include/uapi/linux/elf.h | 2 + tools/perf/tests/bp_signal.c | 2 +- tools/testing/selftests/breakpoints/Makefile | 5 + .../breakpoints/breakpoint_test_riscv.c | 769 +++++++++++++++ 20 files changed, 2874 insertions(+), 53 deletions(-) create mode 100644 arch/riscv/include/asm/hw_breakpoint.h create mode 100644 arch/riscv/kernel/hw_breakpoint.c create mode 100644 arch/riscv/lib/insn.c create mode 100644 tools/testing/selftests/breakpoints/breakpoint_test_riscv.c -- 2.43.0