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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF000397AF.mail.protection.outlook.com (10.167.248.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Wed, 30 Sep 2026 09:26:29 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Wed, 30 Sep 2026 04:26:17 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v6 23/24] iommu/amd: Assign per-vIOMMU translate device ID Date: Wed, 30 Sep 2026 09:23:43 +0000 Message-ID: <20260930092344.5616-24-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260930092344.5616-1-suravee.suthikulpanit@amd.com> References: <20260930092344.5616-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397AF:EE_|PH7PR12MB9222:EE_ X-MS-Office365-Filtering-Correlation-Id: 13484e30-2273-4192-fcd4-08df1ed4e8d8 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|82310400026|23010399003|7416014|376014|36860700016|10067099003|56012099006|11063799006|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: M8th19S22xMSyO0h9Bw/etfiFxsFd68z2MOO9BS4nUiRQS1YsEN36YWMZKPmjitiuFAFcklYL//1TmWYlFnujJ3LSNH8OnDn8F9nbsTpT0FVG/EBEJjbEsPzx5b/FiWbpet97y4qLQEWgeF2YV/uc8qLpP98PF0hSYs1ohvO78/P7kjVaBIqd23MkwvO/ytnIwlRlkdk2wkZW6uxMVrXKE7FRK9nUqfA7ATUmb74EvRlWB5x3FdLEeL/Z17fvH9xLhWuBW5IGrCL908J+vaXcYM8BHaoppeIJOkQAmj7zeaV6ypTmQSQBKTaB9VUPrsYZOXmXP4kYoeuPDrXs9RpWlS4gpQFEN2i548ecq80l+Jz062wZv+uJDBjM8461t/kpxUmYu3gdh29bsuuAjP3DgXiD2EYa6/oh2gpUMMGgAv749ZOGA1BUVcye8xwU1b4 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 09:26:29.7982 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 13484e30-2273-4192-fcd4-08df1ed4e8d8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397AF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9222 Allocate one translate-device-id per IOMMUFD vIOMMU instance from the per-segment pool on init. Reset MMIO first, then program translation DTE and VFctrl TransDevID under trans_devid_lock so PCI-probe relocate cannot interleave. Clear both on init error and destroy, and drop the id before amd_viommu_uninit_one(). Initialize pdom_list before set_translate_dte() so list_empty() is valid. Drop the late list_add; set_translate_dte() already publishes the vIOMMU on viommu_list under pdom->lock. list_del_init() on init error if that add ran. Free the synthetic translate-device-id DTE object on init error and destroy; it is not stored in the per-segment xarray. Add per-vIOMMU trans_devid_lock to serialize DTE and VFctrl TransDevID updates on init and teardown. VFctrl TransDevID is not written from amd_viommu_uninit_one(). Destroy trans_devid_lock on init error and on vIOMMU destroy, after the last unlock, the same way as vfctrl_lock. Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/amd_iommu_types.h | 10 +++++ drivers/iommu/amd/iommufd.c | 68 +++++++++++++++++++++++++---- 2 files changed, 69 insertions(+), 9 deletions(-) diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h index 5f84f25e3f37..c748bab27509 100644 --- a/drivers/iommu/amd/amd_iommu_types.h +++ b/drivers/iommu/amd/amd_iommu_types.h @@ -556,6 +556,16 @@ struct amd_iommu_viommu { /* Synthetic DTE; not stored in pci_seg->dev_data_xa */ struct iommu_dev_data *trans_dev_data; + /* + * Serializes this vIOMMU's translation DTE and VFctrl TransDevID + * updates on init and teardown. VFctrl TransDevID is not written + * from amd_viommu_uninit_one(). + * + * Nested lock order: trans_devid_lock, then + * pci_seg->trans_devid_mutex. + */ + struct mutex trans_devid_lock; + /* * Serializes VFCTRL Guest DID map CONTROL0/CONTROL1 doorbells * (DevID and DomID table updates) for this gid. Those registers diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index 5760b183ce62..1f7485131e63 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -53,6 +53,9 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu, struct iommu_domain * int ret; unsigned long flags; phys_addr_t page_base; + bool trans_devid_allocated = false; + bool trans_dte_set = false; + bool uninit_on_err = false; struct iommu_viommu_amd data = {}; struct protection_domain *pdom = to_pdomain(parent); struct amd_iommu_viommu *aviommu = container_of(viommu, struct amd_iommu_viommu, core); @@ -70,7 +73,9 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu, struct iommu_domain * if (ret) return ret; + mutex_init(&aviommu->trans_devid_lock); mutex_init(&aviommu->vfctrl_lock); + INIT_LIST_HEAD(&aviommu->pdom_list); xa_init_flags(&aviommu->gdomid_array, XA_FLAGS_ALLOC1); aviommu->parent = pdom; @@ -93,35 +98,68 @@ int amd_iommufd_viommu_init(struct iommufd_viommu *viommu, struct iommu_domain * data.out_vfmmio_mmap_offset = aviommu->vfmmio_mmap_offset; - /* Reset vIOMMU MMIOs to initialize the vIOMMU */ + /* Reset vIOMMU MMIOs before the trans_devid is visible in the pool. */ ret = amd_iommu_reset_vmmio(iommu, aviommu->gid); if (ret) - goto err_init; + goto err_trans_devid; + + mutex_lock(&aviommu->trans_devid_lock); + ret = amd_iommu_trans_devid_alloc(iommu->pci_seg, aviommu); + if (ret < 0) { + mutex_unlock(&aviommu->trans_devid_lock); + goto err_trans_devid; + } + trans_devid_allocated = true; + aviommu->trans_devid = ret; + + ret = amd_iommu_set_translate_dte(viommu); + if (ret) + goto err_init_unlock; + trans_dte_set = true; + amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, + aviommu->trans_devid); + mutex_unlock(&aviommu->trans_devid_lock); ret = amd_viommu_init_one(iommu, aviommu); if (ret) goto err_init; + uninit_on_err = true; ret = iommu_copy_struct_to_user(user_data, &data, IOMMU_VIOMMU_TYPE_AMD, out_vfmmio_mmap_offset); if (ret) - goto err_init_one; + goto err_init; viommu->ops = &amd_viommu_ops; - spin_lock_irqsave(&pdom->lock, flags); - list_add(&aviommu->pdom_list, &pdom->viommu_list); - spin_unlock_irqrestore(&pdom->lock, flags); - return 0; -err_init_one: - amd_viommu_uninit_one(iommu, aviommu); err_init: + mutex_lock(&aviommu->trans_devid_lock); +err_init_unlock: + if (trans_dte_set) { + spin_lock_irqsave(&pdom->lock, flags); + if (!list_empty(&aviommu->pdom_list)) + list_del_init(&aviommu->pdom_list); + spin_unlock_irqrestore(&pdom->lock, flags); + amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, 0); + amd_iommu_clear_translate_dte(iommu, aviommu->trans_dev_data, + aviommu->trans_devid); + amd_iommu_free_dev_data(iommu, aviommu->trans_dev_data); + aviommu->trans_dev_data = NULL; + } + if (trans_devid_allocated) + amd_iommu_trans_devid_free(iommu->pci_seg, aviommu->trans_devid, + aviommu); + mutex_unlock(&aviommu->trans_devid_lock); + if (uninit_on_err) + amd_viommu_uninit_one(iommu, aviommu); +err_trans_devid: iommufd_viommu_destroy_mmap(&aviommu->core, aviommu->vfmmio_mmap_offset); err_mmap: amd_iommu_gid_free(iommu, aviommu->gid); err_gid: + mutex_destroy(&aviommu->trans_devid_lock); mutex_destroy(&aviommu->vfctrl_lock); return ret; } @@ -140,8 +178,20 @@ static void amd_iommufd_viommu_destroy(struct iommufd_viommu *viommu) spin_unlock_irqrestore(&pdom->lock, flags); xa_destroy(&aviommu->gdomid_array); iommufd_viommu_destroy_mmap(&aviommu->core, aviommu->vfmmio_mmap_offset); + + mutex_lock(&aviommu->trans_devid_lock); + amd_iommu_update_vfctrl_mmio_translate_devid(iommu, aviommu->gid, 0); + amd_iommu_clear_translate_dte(iommu, aviommu->trans_dev_data, + aviommu->trans_devid); + amd_iommu_free_dev_data(iommu, aviommu->trans_dev_data); + aviommu->trans_dev_data = NULL; + amd_iommu_trans_devid_free(iommu->pci_seg, aviommu->trans_devid, + aviommu); + mutex_unlock(&aviommu->trans_devid_lock); + amd_viommu_uninit_one(iommu, aviommu); amd_iommu_gid_free(iommu, aviommu->gid); + mutex_destroy(&aviommu->trans_devid_lock); mutex_destroy(&aviommu->vfctrl_lock); } -- 2.34.1