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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF000397B0.mail.protection.outlook.com (10.167.248.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Wed, 30 Sep 2026 09:24:29 +0000 Received: from purico-ed03host.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Wed, 30 Sep 2026 04:24:23 -0500 From: Suravee Suthikulpanit To: , , , CC: , , , , , , , , , , , , , , , , , , Suravee Suthikulpanit Subject: [PATCH v6 04/24] iommu/amd: Introduce IOMMUFD vIOMMU support for AMD Date: Wed, 30 Sep 2026 09:23:24 +0000 Message-ID: <20260930092344.5616-5-suravee.suthikulpanit@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260930092344.5616-1-suravee.suthikulpanit@amd.com> References: <20260930092344.5616-1-suravee.suthikulpanit@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B0:EE_|CY3PR12MB9553:EE_ X-MS-Office365-Filtering-Correlation-Id: 6598bba3-f6e7-4012-61f1-08df1ed4a130 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|376014|7416014|1800799024|82310400026|22082099003|18002099003|6133799003|10067099003|56012099006|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: vnliecfJGVq2joooxYBDpIzmjWdjidIg58rCE9bxIMBX6tBwsMsphexqLSx0WubGUiU5tHJ+uiHAC9du/8lJ/IUGc7MnEi3M9DtXLihyeiThpO2bF86Se9Ktf3SvTSU43zOb5BVVjk3slGof/X99MladJHVkzbM1WnTHlS9s+RnvWfNErb3DEAY2q3FbO4EUJeMDmb6nDzT8inflqQv9CjSGH5czGPSOsbLPiu02UcX6upe7ubPqlnrmXpn43oPx2fUtDMZ+RjnnUNLrl94KgyuQdSInQkABxiCNeAJvrdqUk0pEs9+xpLlBX62bbdqT0vp2QZCu1mUCdAtgge3nstRI+LQxLKSkINRVjJEOcTZlBCq4lDsvZT9leNygWfqiTI/Z/mDJcnUAnNSs3pKsBV492cKJ2luXBs7IRS4/yPU2n5+RJWdFvU162T0vWxYT X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 09:24:29.5452 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6598bba3-f6e7-4012-61f1-08df1ed4a130 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY3PR12MB9553 Introduce a new enum iommu_viommu_type (IOMMU_VIOMMU_TYPE_AMD) for AMD vIOMMU along with the struct iommu_viommu_amd, which is used to initialize IOMMUFD vIOMMU instance when calling struct iommu_ops.viommu_init(). Also, hook up struct iomufd_viomu_ops.alloc_domain_nested to connect nested domain allocation with AMD vIOMMU implementation. Only report a non-zero viommu size when the type is AMD and amd_iommu_viommu_enabled() is true for the device's IOMMU. Additional initialization will be added in subsequent patches. Reviewed-by: Jason Gunthorpe Signed-off-by: Suravee Suthikulpanit --- drivers/iommu/amd/iommufd.c | 10 ++++++++++ include/uapi/linux/iommufd.h | 10 ++++++++++ 2 files changed, 20 insertions(+) diff --git a/drivers/iommu/amd/iommufd.c b/drivers/iommu/amd/iommufd.c index 52300b867c1f..e8e7807f2a33 100644 --- a/drivers/iommu/amd/iommufd.c +++ b/drivers/iommu/amd/iommufd.c @@ -34,6 +34,15 @@ void *amd_iommufd_hw_info(struct device *dev, u32 *length, enum iommu_hw_info_ty size_t amd_iommufd_get_viommu_size(struct device *dev, enum iommu_viommu_type viommu_type) { + struct amd_iommu *iommu; + + if (viommu_type != IOMMU_VIOMMU_TYPE_AMD) + return 0; + + iommu = get_amd_iommu_from_dev(dev); + if (!amd_iommu_viommu_enabled(iommu)) + return 0; + return VIOMMU_STRUCT_SIZE(struct amd_iommu_viommu, core); } @@ -73,5 +82,6 @@ static void amd_iommufd_viommu_destroy(struct iommufd_viommu *viommu) * struct iommufd_viommu_ops - vIOMMU specific operations */ static const struct iommufd_viommu_ops amd_viommu_ops = { + .alloc_domain_nested = amd_iommu_alloc_domain_nested, .destroy = amd_iommufd_viommu_destroy, }; diff --git a/include/uapi/linux/iommufd.h b/include/uapi/linux/iommufd.h index 206fa667c782..e1080b997e8f 100644 --- a/include/uapi/linux/iommufd.h +++ b/include/uapi/linux/iommufd.h @@ -1095,6 +1095,7 @@ struct iommu_fault_alloc { * @IOMMU_VIOMMU_TYPE_ARM_SMMUV3: ARM SMMUv3 driver specific type * @IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV: NVIDIA Tegra241 CMDQV (extension for ARM * SMMUv3) enabled ARM SMMUv3 type + * @IOMMU_VIOMMU_TYPE_AMD: AMD HW-vIOMMU type */ enum iommu_viommu_type { IOMMU_VIOMMU_TYPE_DEFAULT = 0, @@ -1105,6 +1106,7 @@ enum iommu_viommu_type { * VMM must wire the HYP_OWN bit to 0 in guest VINTF_CONFIG register */ IOMMU_VIOMMU_TYPE_TEGRA241_CMDQV = 2, + IOMMU_VIOMMU_TYPE_AMD = 3, }; /** @@ -1123,6 +1125,14 @@ struct iommu_viommu_tegra241_cmdqv { __aligned_u64 out_vintf_mmap_length; }; +/** + * struct iommu_viommu_amd - AMD vIOMMU Interface (IOMMU_VIOMMU_TYPE_AMD) + * @out_vfmmio_mmap_offset: (out) mmap offset for vIOMMU VF-MMIO + */ +struct iommu_viommu_amd { + __aligned_u64 out_vfmmio_mmap_offset; +}; + /** * struct iommu_viommu_alloc - ioctl(IOMMU_VIOMMU_ALLOC) * @size: sizeof(struct iommu_viommu_alloc) -- 2.34.1