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Wed, 30 Sep 2026 10:33:10 +0000 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ulf Hansson , Adrian Hunter , Inochi Amaoto , Chen Wang , Jisheng Zhang Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, Philipp Zabel , Changhuang Liang Subject: [PATCH v2 1/2] dt-bindings: mmc: snps,dwcmshc-sdhci: Add starfive,jhb100-dwcmshc Date: Wed, 30 Sep 2026 03:32:57 -0700 Message-Id: <20260930103258.13375-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260930103258.13375-1-changhuang.liang@starfivetech.com> References: <20260930103258.13375-1-changhuang.liang@starfivetech.com> Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: SHXPR01CA0020.CHNPR01.prod.partner.outlook.cn (2406:e500:c311:1b::29) To ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn (2406:e500:c550:17::6) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: ZQ4PR01MB1202:EE_|ZQ4PR01MB1138:EE_ X-MS-Office365-Filtering-Correlation-Id: 253df7f3-b411-4225-9aa0-08df1ede393f X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|23010399003|7416014|376014|52116014|18002099003|22082099003|38350700014|3023799007|10067099003|56012099006; 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The JHB100 controller uses three clocks (core, bus and cclk_tx) and a single reset, so relax the common resets/reset-names minItems from 4 to 1 and add a dedicated conditional schema for the JHB100 compatible that constrains the clocks, clock-names, resets, reset-names and the required starfive,jhb100-per1-syscon property. The property describes the phandle to the PER1 SYSCON and the offset of the register holding the upper DMA address bits [35:32] of the eMMC DMA address, used to extend the default 32-bit DMA capability to 36-bit. Also rework the existing if/else blocks so that the JHB100 compatible is excluded from the branch that requires the extra resets, while keeping the same constraints for the other SoCs. Signed-off-by: Changhuang Liang Reviewed-by: Krzysztof Kozlowski --- .../bindings/mmc/snps,dwcmshc-sdhci.yaml | 74 ++++++++++++++++++- 1 file changed, 70 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index cd823a3ef213..b5cdcc6e8f38 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -32,6 +32,7 @@ properties: - sophgo,cv1800b-dwcmshc - sophgo,sg2002-dwcmshc - sophgo,sg2042-dwcmshc + - starfive,jhb100-dwcmshc - thead,th1520-dwcmshc - eswin,eic7700-dwcmshc @@ -53,11 +54,11 @@ properties: maxItems: 1 resets: - minItems: 4 + minItems: 1 maxItems: 5 reset-names: - minItems: 4 + minItems: 1 maxItems: 5 canaan,usb-phy: @@ -98,6 +99,22 @@ properties: offset of the MSHCCS register used to configure clock synchronisation for HS200 tuning. + starfive,jhb100-per1-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to StarFive JHB100 SoC Peripheral-1 syscon + register block. + - description: Offset of the register used to configure the + upper DMA address bits [35:32] of the eMMC DMA + address. + description: + Phandle to the StarFive JHB100 SoC Peripheral-1 syscon register + block, and the offset of the register that holds the upper DMA + address bits [35:32] of the eMMC DMA address. This is used to + extend the default 32-bit DMA capability of the CMSHC controller + up to 36-bit. + required: - compatible - reg @@ -167,7 +184,16 @@ allOf: - const: core - const: bus - const: timer - else: + + - if: + not: + properties: + compatible: + contains: + enum: + - sophgo,sg2042-dwcmshc + - starfive,jhb100-dwcmshc + then: properties: clocks: minItems: 1 @@ -205,7 +231,16 @@ allOf: required: - eswin,hsp-sp-csr - eswin,drive-impedance-ohms - else: + + - if: + not: + properties: + compatible: + contains: + enum: + - eswin,eic7700-dwcmshc + - starfive,jhb100-dwcmshc + then: properties: resets: minItems: 5 @@ -228,6 +263,37 @@ allOf: required: - power-domains + - if: + properties: + compatible: + contains: + const: starfive,jhb100-dwcmshc + then: + properties: + clocks: + items: + - description: core clock + - description: bus clock + - description: card transmit clock + clock-names: + items: + - const: core + - const: bus + - const: cclk_tx + resets: + maxItems: 1 + reset-names: + items: + - const: core + starfive,jhb100-per1-syscon: true + required: + - resets + - reset-names + - starfive,jhb100-per1-syscon + else: + properties: + starfive,jhb100-per1-syscon: false + unevaluatedProperties: false examples: -- 2.25.1