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Wed, 30 Sep 2026 05:11:48 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Wed, 30 Sep 2026 05:11:43 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Andrea Parri , Boris Pismenny , Carolina Jubran , Cosmin Ratiu , Dragos Tatulea , Fernando Fernandez Mancera , Gal Pressman , Jianbo Liu , Kees Cook , Leon Romanovsky , open list , , Mark Bloch , Parav Pandit , Patrisious Haddad , Raed Salem , Roi Dayan , Saeed Mahameed , Steffen Klassert , "Tariq Toukan" Subject: [PATCH net V2 0/4] net/mlx5e: Fix offload lifetime and exclusion bugs Date: Wed, 30 Sep 2026 15:11:15 +0300 Message-ID: <20260930121119.141953-1-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PEPF0000000F:EE_|BN7PPF9507C739C:EE_ X-MS-Office365-Filtering-Correlation-Id: f4d9b70d-6611-4b59-a5d8-08df1eec0e66 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|7416014|82310400026|1800799024|376014|36860700016|13003099007|10067099003|11063799006|56012099006|18002099003; X-Microsoft-Antispam-Message-Info: 9HD43n1Dq8vzV7MKpmkKgIKYZHBHEk5gKTMwxeq6WF8BVMHLgtFR1b+6YNwRFunTMA0gqGl2To4Bk5JDL8WP/dervN/gCOeb7D3/kC4RfHmf5ihUC/fOSnoewDFRKbuaXR+JScqADXYypP8EIcJZ4mn/tK2fHVq6qX7GZwRLzwTSIAG1D0nAwJaUIcD47+Rl/m/36UOr6jBFWolv9l+07gzi6iRF87+1z9U3tWLQTU9p49Ut/iKxQtOEazLBZJaw8F5wz3nDlDCE6yAUmaaOO/0nqMMnsQEMayGeBjU0y39ZwLLy3P4DkL/ywB25MugM5IFcdWABM+1bGKOM47KXX7ufXRGuSrqBo/ClldDvGs7DTUhk7323ILHKno0td34O8POKKPPFW3fGOdV2DMEtA+PmS/zMgoroHQ0R0HBJF1LaeJXyPZOk3Ac5R3iXoUBEOYkt2AizmRBvOG88+R7Ua38bE8INZIiokV76mXBirHJFMGmXJg+bb0dr//P9jQYKQKf8Js6If5GDpyEqljRHeZgZUnKGoIwZx2p7dg64elMZNRydgr5lFyldVoboRweCVIUcfH+qvXDhNaKDmnVrbh0/7SvFTWyJGPwyzrAgFXEVUH95yqPoJ8rTrfw4oLkNc99r7w+7YR0J7+AFhgYMj94TuNSUJYVpDulfadTfreTUcw2yoayQGUpVgtAnEdJdfHcLNh7n2UjKkOadPmpdSg== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(7416014)(82310400026)(1800799024)(376014)(36860700016)(13003099007)(10067099003)(11063799006)(56012099006)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: m8ly3k/W53GLJsb81XXn+6G8q1OhpfhkO0fxuYd/IdILOY9AIUkZ7U2yvZUrWJoW7+Coa4v3tBIP5166hLHq2ogXvCJf7d8fFyrPaKCrqjS6CEBYll4h3gcmXbTRGxdN6YEZsgmI+E+r6L/YuOcQ4avp3Lwd8tIUISzUYyp7cHm6kctZDDc5S646abco+xhYAs78R740EKIjUJE0ihZcmDOcc0nYRlTzpqYUabeCz8wFaTYR4QWQRv+V5HZzF00nLobEHGBjlORyaeqolLi7tH/nIAvTB3DNnZ9FJJuTxqr8JD8xz9EU/qORtVFzGK+aAdESAsVL75FwLWarcWvSyWRY15gLaZwfai0lJk1DgH3kMGEeGW5lqMpT5PlX0r4ISKmTeKTvAD3yiLY5vJ73fhJwRnI4ZCsVtufRVsGzIFDEQun5kX5+F7rhr5WoWwrY X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Sep 2026 12:12:11.0936 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4d9b70d-6611-4b59-a5d8-08df1eec0e66 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CH3PEPF0000000F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF9507C739C Hi, This series by Cosmin fixes several mlx5e offload issues: - Block eswitch mode changes before accessing the IPsec context during policy and SA creation. - Tie TC eswitch and IPsec-blocking references to flow destruction, covering bulk cleanup and flows with outstanding references. - Serialize TC/IPsec exclusion counters with a dedicated mutex. Regards, Tariq V2: - Use mlx5_esw_lock() in mlx5_eswitch_block_mode() (Sashiko) - Clarified the fix split across first two patches (Sashiko) - More careful dereferencing priv->mdev in mlx5e_xfrm_add_state() (Sashiko) - Avoided spurious error message during IPsec SW fallback (Sashiko) - Harmonized check_users arg for policy & state add (Sashiko) - Clarified the scope of the "tc: tie..." fix (Sashiko) - Moved macsec patches into a separate series. V1: https://lore.kernel.org/netdev/20260917175433.4090878-1-tariqt@nvidia.com/ Cosmin Ratiu (4): net/mlx5e: ipsec: Block eswitch mode changes during policy creation net/mlx5e: ipsec: Block eswitch mode changes before accessing priv->ipsec net/mlx5e: Serialize TC and IPsec offload exclusion counters net/mlx5e: tc: Tie esw & accel blocking refs to the flow's lifetime .../mellanox/mlx5/core/en_accel/ipsec.c | 65 +++++++++++++----- .../mellanox/mlx5/core/en_accel/ipsec_fs.c | 47 ++++--------- .../net/ethernet/mellanox/mlx5/core/en_tc.c | 66 ++++++++++++------- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 11 ++-- .../net/ethernet/mellanox/mlx5/core/eswitch.h | 10 ++- .../mellanox/mlx5/core/eswitch_offloads.c | 7 +- .../net/ethernet/mellanox/mlx5/core/main.c | 3 + include/linux/mlx5/driver.h | 7 +- 8 files changed, 128 insertions(+), 88 deletions(-) base-commit: 99b43ede9e355ba35244cc9470bf1819774ce39d -- 2.44.0