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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-34cf5639339sm4524609eec.18.2026.09.30.07.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 07:52:18 -0700 (PDT) From: Georgi Djakov To: andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, minchan@kernel.org, senozhatsky@chromium.org Cc: axboe@kernel.dk, rostedt@goodmis.org, mhiramat@kernel.org, mathieu.desnoyers@efficios.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-block@vger.kernel.org, linux-trace-kernel@vger.kernel.org, djakov@kernel.org Subject: [PATCH 0/6] soc: qcom: Add Qualcomm Page Compression Engine (QPaCE) driver Date: Wed, 30 Sep 2026 07:52:09 -0700 Message-Id: <20260930145215.3380977-1-georgi.djakov@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: 9bZjJaCWr9dBnIZTr5L8w3sjPqOzZZdo X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTMwMDA1OSBTYWx0ZWRfX/18R5Af5j3On lQBReNToLE6aCKEJ3/mDjOKlM+mU8p7j6Myj3dep5LHNgGyKfeV0/eAkOG27Y/i6axGcJA/mVnK mlqZ1DfMhdpsBRWNBXYNzUyL44yhTwWZqA+K/qb9Yu9dXfZAvHotCzSigCqI76hXaEC6tWPa0bb itEqE5wIz3YtwpQWOBNgKlvP609NOiIgl6EL0QTADq+iJmD3LYNIMnM2k28r44ODIG8GmHcJtvv 8muEo36ZS0I9XR/Hj2urtwNO/2hrj+/8ShGru4CvSNKdxCwZObpKxrAFFf3v1pxg+hLhlu0Zv3s /xEPN9sWZYDeoiJOQcYwkvDG0DL8LClzqrPDDMPnOKG+014fkdIIdXT2QdUZhcy4RGzg9X6j3WD CNY4eMbkxfOab/iotSxOkPP/XL8IOrXeEexZsoou0PeUncgFBD9gie6UZX96UPIXYllIeDNKkdS 2RYxszs2aYysFY89E9g== X-Authority-Analysis: v=2.4 cv=MZn5KJ/f c=1 sm=1 tr=0 ts=6abd2225 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=oM0TwoE6PClt58MffhQA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTMwMDA1OSBTYWx0ZWRfX8XRmek/z6RcI RqTKgrAy3JsrYx/cdOmqLpFmNQ7xOrFbOVKY8BbUuPfkw8x6La/m+/7E+/c/YhMAD/y9UAioC1H HtbVx85oWzZdNDm/2x02UWbXFiuLQLc= X-Proofpoint-ORIG-GUID: 9bZjJaCWr9dBnIZTr5L8w3sjPqOzZZdo X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-30_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 clxscore=1011 impostorscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609300059 QPaCE (Qualcomm Page Compression Engine) is a hardware block found on Qualcomm SoCs that accelerates page compression and decompression for use with the zram block device. It is composed of multiple compression, decompression, and copy engines. This series uses QPaCE's "urgent" (synchronous) path, intended for low- latency single-page operations. A command is issued by writing the source and destination DMA addresses to one of several per-CPU urgent command registers with a single store; completion is then detected by polling the command's status register. The hardware also provides a ring-based (asynchronous) path for high- throughput batched compression, where transfer and event rings allow multiple descriptors to be queued and submitted with a single doorbell write, with completion signalled via an interrupt. This path is not implemented in this series. The driver integrates with zram through a new "qpace-lz4" zcomp backend. Both compression and decompression are performed by the QPaCE hardware via the urgent synchronous path: each request DMA-maps the source and destination buffers, issues a blocking hardware command, and returns the result size. The driver also integrates with the Qualcomm Last Level Cache Controller (LLCC) to activate dedicated cache slices for compression and decompression data. This is validated on next-20260929 with the following patch applied on top to allow booting completely to the serial console: https://lore.kernel.org/all/20260911-rsc_read-v2-1-98675c248278@oss.qualcomm.com/ Georgi Djakov (6): dt-bindings: soc: qcom: Add QPaCE binding soc: qcom: qpace: Add Qualcomm Page Compression Engine driver trace: qpace: Add tracepoints for QPaCE operations zram: Add QPaCE zcomp backend soc: qcom: qpace: Add LLCC slice support arm64: dts: qcom: hawi: Add QPaCE DT node .../bindings/soc/qcom/qcom,hawi-qpace.yaml | 94 ++ arch/arm64/boot/dts/qcom/hawi.dtsi | 17 + drivers/block/zram/Kconfig | 11 + drivers/block/zram/Makefile | 1 + drivers/block/zram/backend_qpace.c | 134 +++ drivers/block/zram/backend_qpace.h | 13 + drivers/block/zram/zcomp.c | 11 +- drivers/soc/qcom/Kconfig | 14 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/qpace.c | 830 ++++++++++++++++++ drivers/soc/qcom/qpace_internal.h | 84 ++ include/linux/soc/qcom/llcc-qcom.h | 2 + include/linux/soc/qcom/qpace.h | 154 ++++ include/trace/events/qpace.h | 99 +++ 14 files changed, 1463 insertions(+), 2 deletions(-) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,hawi-qpace.yaml create mode 100644 drivers/block/zram/backend_qpace.c create mode 100644 drivers/block/zram/backend_qpace.h create mode 100644 drivers/soc/qcom/qpace.c create mode 100644 drivers/soc/qcom/qpace_internal.h create mode 100644 include/linux/soc/qcom/qpace.h create mode 100644 include/trace/events/qpace.h