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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-34cf5639339sm4524609eec.18.2026.09.30.07.52.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 07:52:20 -0700 (PDT) From: Georgi Djakov To: andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, minchan@kernel.org, senozhatsky@chromium.org Cc: axboe@kernel.dk, rostedt@goodmis.org, mhiramat@kernel.org, mathieu.desnoyers@efficios.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-block@vger.kernel.org, linux-trace-kernel@vger.kernel.org, djakov@kernel.org Subject: [PATCH 1/6] dt-bindings: soc: qcom: Add QPaCE binding Date: Wed, 30 Sep 2026 07:52:10 -0700 Message-Id: <20260930145215.3380977-2-georgi.djakov@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260930145215.3380977-1-georgi.djakov@oss.qualcomm.com> References: <20260930145215.3380977-1-georgi.djakov@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: G2fpWx6ARO16qU3o3d980Z2V3BIsknUe X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTMwMDA1OSBTYWx0ZWRfX/nfaYWXhzVzn 9uw9ZTww3wKvFT0mPNWvdhYO23x7km687oN/XmeoEX5X5bzBjyNQxhl8528WgZ58FKGaVXyp97C F3j4zfc/iI24m9tsyUDdShfbKZOHxMVBzzQ3O5nepXWyIatO12sg8Xiqa8hlYXHnowVhFRQ8acZ Nqu7PodLnkwNZXNj7sD9lUy8aYoED8m7GDGoqR28Fg1PaK6QzyKYcETHwL9EQW37FQseJArN79C mX2bZqTWBuhBAKY5sVVvumLs2H6dadZmUUiNE8EUgyEoeEzC4OFRABmvuTmHYiWgBDDDBcupoUT cDeJtVqrBqmQQpqsE0ShZnPezc92SzMUqnwhlRzWOu71xMXlRd62PRHOpgfF45trrE8iF47f9Dg kpjonP158YY7jj1EKh+jrkAujrCWw2xB2I41NzOUbdFu1kZjwCHHFNWK3f1EGhnaqbWLIVdpa2B VBmKtTnpUUgVG/sS8lQ== X-Authority-Analysis: v=2.4 cv=MZn5KJ/f c=1 sm=1 tr=0 ts=6abd2226 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=gEfo2CItAAAA:8 a=EUspDBNiAAAA:8 a=P4ADLzTW1IxIBgx77pIA:9 a=6Ab_bkdmUrQuMsNx7PHu:22 a=sptkURWiP4Gy88Gu7hUp:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTMwMDA1OSBTYWx0ZWRfX/f2CnSJF2x3J 3Gi1j81K6MXzsRRbRwDB9OAcuuxpjpjKYo4K3erzIKHVdXaEQZKFqhaG4N1HibMsVcKShtiykOi X5UFkk6hSEK45xqCw/axMLuYMnZ7FTI= X-Proofpoint-ORIG-GUID: G2fpWx6ARO16qU3o3d980Z2V3BIsknUe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-30_03,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609300059 Add device-tree binding documentation for the Qualcomm Page Compression Engine (QPaCE), including the resources needed to describe it in SoC device trees. QPaCE accelerates page compression and decompression for use with the zram block device. Signed-off-by: Georgi Djakov --- .../bindings/soc/qcom/qcom,hawi-qpace.yaml | 94 +++++++++++++++++++ 1 file changed, 94 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,hawi-qpace.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,hawi-qpace.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,hawi-qpace.yaml new file mode 100644 index 000000000000..b7ae50f34f16 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,hawi-qpace.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,hawi-qpace.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Page Compression Engine (QPaCE) + +maintainers: + - Georgi Djakov + +description: + QPaCE is a page-oriented hardware compression engine found on Qualcomm + SoCs. It is composed of a number of compression, decompression and copy + engines and exposes both a low-latency urgent path for synchronous + single-page operations and a high-throughput ring-based path for batched + asynchronous requests. + +properties: + compatible: + items: + - enum: + - qcom,hawi-qpace + + reg: + maxItems: 1 + description: + Single contiguous register window covering all QPaCE sub-regions + from the GEN registers base through the EE registers. + + iommus: + items: + - description: IOMMU mapping for compression engine read DMA + - description: IOMMU mapping for compression engine write DMA + - description: IOMMU mapping for decompression engine read DMA + - description: IOMMU mapping for decompression engine write DMA + + dma-coherent: true + + interconnects: + maxItems: 1 + + interconnect-names: + items: + - const: qpace-mem + + interrupts: + items: + - description: Ring completion and bus error interrupt + - description: Urgent command completion interrupt + + interrupt-names: + items: + - const: ring-and-bus-err + - const: urgent + +required: + - compatible + - reg + - iommus + - interconnects + - interconnect-names + - interrupts + - interrupt-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + compression@31400000 { + compatible = "qcom,hawi-qpace"; + reg = <0x0 0x31400000 0x0 0x80000>; + iommus = <&apps_smmu 0x1c20 0x13>, + <&apps_smmu 0x1c24 0x13>, + <&apps_smmu 0x1c28 0x13>, + <&apps_smmu 0x1c2c 0x13>; + dma-coherent; + interconnects = <&gem_noc MASTER_QPACE QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qpace-mem"; + interrupts = , + ; + interrupt-names = "ring-and-bus-err", + "urgent"; + }; + };