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[83.233.221.82]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2e31d867ffsm57071466b.59.2026.09.30.14.23.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 14:23:59 -0700 (PDT) From: Yongzhao Chen To: Andrew Lunn Cc: netdev@vger.kernel.org, Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next] net: phy: qca83xx: read resolved QCA8337 link status Date: Wed, 30 Sep 2026 23:23:47 +0200 Message-ID: <20260930212348.1919-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <01a62e77-6c4e-4665-ba46-26d12b1c77b4@lunn.ch> References: <20260928220749.857-1-yongzhao.derek@gmail.com> <01a62e77-6c4e-4665-ba46-26d12b1c77b4@lunn.ch> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Hi Andrew,=0D =0D > If there is no link, genphy_read_status() will of already set these to=0D > _UNKNOWN etc. There is no need to clear them.=0D =0D Right, thanks. In the next revision I have replaced the custom decoding=0D and state clearing with at803x_read_status(), followed by=0D genphy_read_master_slave() to keep the master/slave reporting from the=0D generic path.=0D =0D > Can this really happen? BCMR says there is link, but this says there=0D > is no link? What does the data sheet say? It seems unlikely to me.=0D =0D I have not observed it on hardware. The QCA8337 datasheet (80-Y0619-3=0D Rev. D, p. 328) describes the resolved bit and the speed/duplex fields=0D in register 0x11, and says speed/duplex are valid after autonegotiation=0D completes. I could not find anything there about the ordering of that=0D bit and the BMSR link status across separate reads. The unresolved case=0D in my test was synthetic input, not a state captured on hardware.=0D =0D In that synthetic sequence, at803x_read_status() reports link up with=0D SPEED_UNKNOWN. If BMSR stays up when 0x11 later resolves, the speed=0D remains SPEED_UNKNOWN until the next link transition. So switching to=0D the helper does not by itself answer whether this state can occur on=0D real hardware. Is there a QCA8337-specific rule about when register 0x11=0D is updated relative to BMSR that I should check before deciding whether=0D this needs separate handling?=0D =0D Separately, I have not yet reproduced on hardware the case this patch=0D targets, a QCA8337-side SmartSpeed downshift where the old code reports=0D the wrong speed; so far that difference is only shown by the model test.=0D With a two-pair cable, the link partner advertised gigabit and then=0D withdrew it, and the link came up at 100 Mb/s without the QCA8337=0D downshift status set.=0D =0D If you know of a link partner or setup that reliably makes the QCA8337=0D side downshift, I would be glad to test with it.=0D =0D Thanks,=0D Yongzhao Chen=0D