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[83.233.221.82]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c2e31a35d61sm57600366b.10.2026.09.30.14.24.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Sep 2026 14:24:24 -0700 (PDT) From: Yongzhao Chen To: Christian Marangi Cc: netdev@vger.kernel.org, Ziyang Huang , Andrew Lunn , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Florian Fainelli , linux-kernel@vger.kernel.org Subject: Re: [PATCH net-next v4 3/3] net: dsa: qca8k: support QCA8337 internal PHY CPU links Date: Wed, 30 Sep 2026 23:24:12 +0200 Message-ID: <20260930212412.1973-1-yongzhao.derek@gmail.com> X-Mailer: git-send-email 2.45.2.windows.1 In-Reply-To: <6abb54ff.332d3c56.21546b.7fef@mx.google.com> References: <20260928220811.1880-1-yongzhao.derek@gmail.com> <20260928220811.1880-4-yongzhao.derek@gmail.com> <6abb54ff.332d3c56.21546b.7fef@mx.google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Hi Christian,=0D =0D Thanks for the review.=0D =0D > Can you put an example DT for this? Also no additional register are neede= d=0D > to this special mode?=0D =0D Here is an example using the switch's internal MDIO bus, with the other=0D user ports omitted. The SoC MAC has its own PHY at the other end of the=0D PHY-to-PHY connection; its phy-mode must follow that MAC's binding. The=0D full example passed dtc and the qca8k binding check.=0D =0D switch@10 {=0D compatible =3D "qca,qca8337";=0D reg =3D <0x10>;=0D =0D ports {=0D #address-cells =3D <1>;=0D #size-cells =3D <0>;=0D =0D port@1 {=0D reg =3D <1>;=0D label =3D "lan1";=0D phy-mode =3D "internal";=0D phy-handle =3D <&switch_phy0>;=0D };=0D =0D port@5 {=0D reg =3D <5>;=0D ethernet =3D <&soc_mac>;=0D phy-mode =3D "internal";=0D phy-handle =3D <&switch_phy4>;=0D };=0D };=0D =0D mdio {=0D #address-cells =3D <1>;=0D #size-cells =3D <0>;=0D switch_phy0: ethernet-phy@0 { reg =3D <0>; };=0D switch_phy4: ethernet-phy@4 { reg =3D <4>; };=0D };=0D };=0D =0D I did not add any register writes for this mode: qca8k_setup() already=0D programs header mode for the CPU port, the four GLOBAL_FW_CTRL1=0D destination masks, and the CPU/user membership masks using the selected=0D port. CPU_PORT_EN remains set by the existing setup code; I have not=0D tested clearing it.=0D =0D I tested port 5 as the only CPU port on a Redmi AX5400 (RA74) with an=0D OpenWrt Linux 6.18.52 backport. Readback showed header mode only on=0D port 5 and all four destination masks selecting port 5. BPDU, LLDP,=0D EAPOL-Start and broadcast ARP frames arrived intact in both directions,=0D and unknown unicast/multicast flooding toward the CPU, DHCP, MTU=0D changes, renegotiation and ping also passed.=0D =0D That test used the external MDIO bus with wireless disabled, and needed=0D two workarounds that are not in the posted series: a dummy phy-handle on=0D port 6 (a fixed-link user port) for MDIO classification, and a NULL-PHY=0D guard in qca8k_port_enable(). So it does not validate the internal-MDIO=0D example above on hardware. I will reword the commit message in the next=0D revision to claim only what was tested.=0D =0D Would you prefer the fixed-link NULL-PHY handling to be addressed in a=0D separate prerequisite patch? The guard skips phy_support_asym_pause()=0D when phy is NULL, as it is for a fixed-link user port. For port 5, are=0D there other CPU-port registers or traffic paths you would want checked,=0D or is testing the internal-MDIO configuration on hardware the main gap?=0D =0D Thanks,=0D Yongzhao Chen=0D