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Use them. Signed-off-by: Andrew Davis --- drivers/i2c/busses/i2c-omap.c | 82 +++++++++++++++++------------------ 1 file changed, 41 insertions(+), 41 deletions(-) diff --git a/drivers/i2c/busses/i2c-omap.c b/drivers/i2c/busses/i2c-omap.c index 5d5a237c07a5e..c83f6a4d4b097 100644 --- a/drivers/i2c/busses/i2c-omap.c +++ b/drivers/i2c/busses/i2c-omap.c @@ -79,64 +79,64 @@ enum { }; /* I2C Status bits (OMAP_I2C_IE, OMAP_I2C_STAT, OMAP_I2C_WE) */ -#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */ -#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */ -#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */ -#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */ -#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */ -#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */ -#define OMAP_I2C_STAT_BF (1 << 8) /* Bus Free */ -#define OMAP_I2C_STAT_STC (1 << 6) /* Start condition */ -#define OMAP_I2C_STAT_GC (1 << 5) /* General call */ -#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */ -#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */ -#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */ -#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack */ -#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost */ +#define OMAP_I2C_STAT_XDR BIT(14) /* TX Buffer draining */ +#define OMAP_I2C_STAT_RDR BIT(13) /* RX Buffer draining */ +#define OMAP_I2C_STAT_BB BIT(12) /* Bus busy */ +#define OMAP_I2C_STAT_ROVR BIT(11) /* Receive overrun */ +#define OMAP_I2C_STAT_XUDF BIT(10) /* Transmit underflow */ +#define OMAP_I2C_STAT_AAS BIT(9) /* Address as slave */ +#define OMAP_I2C_STAT_BF BIT(8) /* Bus Free */ +#define OMAP_I2C_STAT_STC BIT(6) /* Start condition */ +#define OMAP_I2C_STAT_GC BIT(5) /* General call */ +#define OMAP_I2C_STAT_XRDY BIT(4) /* Transmit data ready */ +#define OMAP_I2C_STAT_RRDY BIT(3) /* Receive data ready */ +#define OMAP_I2C_STAT_ARDY BIT(2) /* Register access ready */ +#define OMAP_I2C_STAT_NACK BIT(1) /* No ack */ +#define OMAP_I2C_STAT_AL BIT(0) /* Arbitration lost */ /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */ -#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */ -#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */ -#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */ -#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */ +#define OMAP_I2C_BUF_RDMA_EN BIT(15) /* RX DMA channel enable */ +#define OMAP_I2C_BUF_RXFIF_CLR BIT(14) /* RX FIFO Clear */ +#define OMAP_I2C_BUF_XDMA_EN BIT(7) /* TX DMA channel enable */ +#define OMAP_I2C_BUF_TXFIF_CLR BIT(6) /* TX FIFO Clear */ /* I2C Configuration Register (OMAP_I2C_CON): */ -#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */ -#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */ -#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */ -#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */ -#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */ -#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */ -#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */ -#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */ -#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */ -#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */ +#define OMAP_I2C_CON_EN BIT(15) /* I2C module enable */ +#define OMAP_I2C_CON_BE BIT(14) /* Big endian mode */ +#define OMAP_I2C_CON_OPMODE_HS BIT(12) /* High Speed support */ +#define OMAP_I2C_CON_STB BIT(11) /* Start byte mode (master) */ +#define OMAP_I2C_CON_MST BIT(10) /* Master/slave mode */ +#define OMAP_I2C_CON_TRX BIT(9) /* TX/RX mode (master only) */ +#define OMAP_I2C_CON_XA BIT(8) /* Expand address */ +#define OMAP_I2C_CON_RM BIT(2) /* Repeat mode (master only) */ +#define OMAP_I2C_CON_STP BIT(1) /* Stop cond (master only) */ +#define OMAP_I2C_CON_STT BIT(0) /* Start condition (master) */ /* I2C SCL time value when Master */ #define OMAP_I2C_SCLL_HSSCLL 8 #define OMAP_I2C_SCLH_HSSCLH 8 /* I2C System Test Register (OMAP_I2C_SYSTEST): */ -#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */ -#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */ -#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */ +#define OMAP_I2C_SYSTEST_ST_EN BIT(15) /* System test enable */ +#define OMAP_I2C_SYSTEST_FREE BIT(14) /* Free running mode */ +#define OMAP_I2C_SYSTEST_TMODE_MASK GENMASK(13, 12) /* Test mode select */ #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */ /* Functional mode */ -#define OMAP_I2C_SYSTEST_SCL_I_FUNC (1 << 8) /* SCL line input value */ -#define OMAP_I2C_SYSTEST_SCL_O_FUNC (1 << 7) /* SCL line output value */ -#define OMAP_I2C_SYSTEST_SDA_I_FUNC (1 << 6) /* SDA line input value */ -#define OMAP_I2C_SYSTEST_SDA_O_FUNC (1 << 5) /* SDA line output value */ +#define OMAP_I2C_SYSTEST_SCL_I_FUNC BIT(8) /* SCL line input value */ +#define OMAP_I2C_SYSTEST_SCL_O_FUNC BIT(7) /* SCL line output value */ +#define OMAP_I2C_SYSTEST_SDA_I_FUNC BIT(6) /* SDA line input value */ +#define OMAP_I2C_SYSTEST_SDA_O_FUNC BIT(5) /* SDA line output value */ /* SDA/SCL IO mode */ -#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */ -#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */ -#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */ -#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */ +#define OMAP_I2C_SYSTEST_SCL_I BIT(3) /* SCL line sense in */ +#define OMAP_I2C_SYSTEST_SCL_O BIT(2) /* SCL line drive out */ +#define OMAP_I2C_SYSTEST_SDA_I BIT(1) /* SDA line sense in */ +#define OMAP_I2C_SYSTEST_SDA_O BIT(0) /* SDA line drive out */ /* OCP_SYSSTATUS bit definitions */ -#define OMAP_I2C_SYSS_RESETDONE (1 << 0) +#define OMAP_I2C_SYSS_RESETDONE BIT(0) /* OCP_SYSCONFIG bit definitions */ -#define OMAP_I2C_SYSC_SOFTRESET (1 << 1) +#define OMAP_I2C_SYSC_SOFTRESET BIT(1) /* Errata definitions */ #define I2C_OMAP_ERRATA_I207 (1 << 0) -- 2.39.2