From: Ali Rouhi <arouhi@sitime.com>
To: "kuba@kernel.org" <kuba@kernel.org>
Cc: Jiri Pirko <jiri@resnulli.us>,
Vadim Fedorenko <vadim.fedorenko@linux.dev>,
Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>,
Ivan Vecera <ivecera@redhat.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Carolina Jubran <cjubran@nvidia.com>,
Oleg Zadorozhnyi <Oleg.Zadorozhnyi@devoxsoftware.com>,
Paolo Abeni <pabeni@redhat.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v10 03/14] dpll: add basic SiTime SiT9531x support
Date: Wed, 30 Sep 2026 23:33:15 +0000 [thread overview]
Message-ID: <20260930233306.81858-2-arouhi@sitime.com> (raw)
In-Reply-To: <20260926023441.1567546-1-kuba@kernel.org>
On Fri, 25 Sep 2026, Jakub Kicinski wrote:
> [Severity: Low]
> At this commit, can SIT9531X_DPLL build anything unless some other driver
> selects DPLL?
>
> DPLL is a hidden bool that has no prompt. If SIT9531X_DPLL is the only DPLL
> user in a config, the line
>
> obj-$(CONFIG_SIT9531X_DPLL) += sit9531x/
>
> is never evaluated, and no sit9531x object or module gets built.
Fixed. "select DPLL" now sits in this patch's Kconfig rather than in
"dpll: sit9531x: register DPLL devices and pins", so this commit builds
what it adds and the series is bisectable for build coverage as well as
for correctness. Deferring the select was deliberate in v10 and it was
the wrong call.
> [Severity: Medium]
> Can the cached page selector get out of sync with the chip, and then stay
> that way?
>
> Suppose i2c_smbus_write_byte_data() fails for the selector write. The error
> comes back, but the cached value is not dropped. The raw write path in
> _regmap_raw_write_impl() does drop it with map->cache_ops->drop(). The chip
> then stays on page A while the cache says page B.
>
> Would a selector reset on the chip side also go uncorrected, for example
> power loss across suspend or an internal reload?
Both cases are real and both are handled in v11.
sit9531x_page_cache_drop() wraps regcache_drop_region() on the selector
and is called from four places: on failure in sit9531x_read_u8(), on
failure in sit9531x_write_u8(), on failure in sit9531x_update_pll_u8(),
and at the top of sit9531x_resume(). The first three cover the failed
transfer, the last covers a part that lost the selector across suspend.
The next access after any of them re-selects the page instead of
trusting the cache.
sit9531x_update_pll_u8() is worth calling out because it was not
covered by the first version of this fix. It computes the virtual
address itself and calls regmap_update_bits() directly, and a
read-modify-write is a read and a write, so either half can leave the
selector wrong. It now fails the way the single accessors do.
One thing your description gets at that is worth stating for the next
reader of this code: the missing drop is not ours to add here. It is in
regmap core, in _regmap_write(), which updates the cache before the bus
write and does not undo that on error, while _regmap_raw_write_impl()
does call map->cache_ops->drop(). So the asymmetry is between the two
write paths in regmap, and on adapters limited to SMBus byte data we
get the one without the drop. v11 works around it rather than fixing
it, which we think is the right scope for a new driver, but the
workaround should not read as belt-and-braces to whoever touches it
next.
> The comment says the selector is something "only this driver moves". Does
> that still hold once a transfer fails or the chip resets?
It does not, and the comment no longer says it.
> [Severity: Low]
> This isn't a bug, but is this message meant to print the regmap virtual
> address rather than the SIT9531X_REG(page, offset) value the caller passed
> in?
>
> For example, a failed VARIANT_ID read, SIT9531X_REG(0x00, 0x02) = 0x0002,
> is logged as "reg 0x0102", which looks like page 1, offset 0x02.
Fixed, and taken a little further than keeping the original value. The
translated address goes into a separate variable, so reg stays intact,
and the messages now print the two fields separately:
"Failed to read page 0x%02x reg 0x%02x: %d\n"
"Failed to write page 0x%02x reg 0x%02x: %d\n"
A failed VARIANT_ID read reports page 0x00 reg 0x02, with nothing left
for the reader to decode.
This patch is patch 4 of v11.
Ali
next prev parent reply other threads:[~2026-09-30 23:33 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-21 20:11 [PATCH v10 00/14] dpll: add SiTime SiT9531x DPLL clock driver Ali Rouhi
2026-09-21 20:11 ` [PATCH v10 01/14] dt-bindings: vendor-prefixes: add SiTime Corporation Ali Rouhi
2026-09-21 20:11 ` [PATCH v10 02/14] dt-bindings: dpll: add SiTime SiT95316 clock generator Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-30 23:33 ` Ali Rouhi
2026-09-21 20:11 ` [PATCH v10 03/14] dpll: add basic SiTime SiT9531x support Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-30 23:33 ` Ali Rouhi [this message]
2026-09-21 20:11 ` [PATCH v10 04/14] dpll: sit9531x: read DPLL types and pin properties from system firmware Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 05/14] dpll: sit9531x: register DPLL devices and pins Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 06/14] dpll: sit9531x: implement input pin state on a DPLL Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-30 23:33 ` Ali Rouhi
2026-09-21 20:11 ` [PATCH v10 07/14] dpll: sit9531x: add support to get and set priority on input pins Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 08/14] dpll: sit9531x: add support to get and set frequency on pins Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 09/14] dpll: sit9531x: implement output pin state on a DPLL Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 10/14] dpll: sit9531x: add support to adjust output phase Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 11/14] dpll: sit9531x: add support to get phase offset on the connected input pin Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 12/14] dpll: sit9531x: add support to get fractional frequency offset Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 13/14] dpll: sit9531x: model the inter-PLL sync net as a pair of pins Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-21 20:11 ` [PATCH v10 14/14] dpll: sit9531x: allow the device tree to override two board facts Ali Rouhi
2026-09-26 2:34 ` Jakub Kicinski
2026-09-28 23:29 ` [PATCH v10 00/14] dpll: add SiTime SiT9531x DPLL clock driver Jakub Kicinski
2026-09-29 0:38 ` Ali Rouhi
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260930233306.81858-2-arouhi@sitime.com \
--to=arouhi@sitime.com \
--cc=Oleg.Zadorozhnyi@devoxsoftware.com \
--cc=arkadiusz.kubalewski@intel.com \
--cc=cjubran@nvidia.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=ivecera@redhat.com \
--cc=jiri@resnulli.us \
--cc=krzk+dt@kernel.org \
--cc=kuba@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=robh@kernel.org \
--cc=vadim.fedorenko@linux.dev \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®