From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from Atcsqr.andestech.com (atcsqr.andestech.com [220.128.198.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A9BA35C1A6; Thu, 1 Oct 2026 02:12:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=220.128.198.184 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790820743; cv=none; b=rHVG5rxYLPu08ZvdnDQXp+pNypbVONAh83de6Q8at0iapB5cotQK6xAi63lx/DtoyAuRbU8ViLX23gJzRliFlZsj0uCzLtjZ0JpHEQWpYvtXbAOLArKWQoSSlvBIGKVDNpxtlAFnahGYBtFUwdRe7GzwFt6EAuwtH8inYxbTVq4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790820743; c=relaxed/simple; bh=0paWo37tIwXwNgKO9+QqBch1+DRgfGnkuF/C5gAnmkk=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=IosCnNvHH/GETsPkog/55g+wm+c6wWu8Pz0uNK6ztqhKgTECVNR2Pugafgx8z/8QDTJDsOq/aaZ+BnYDUpjve6ZRI01+9ERNGZd++PbPagEOLR5vq7JaVp6ECfCW9oYsiHvjFBzEFUMsljhSkSSdy1az5sjcP1EQYpJQUQsOo14= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=220.128.198.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from Atcsqr.andestech.com (localhost [127.0.0.2] (may be forged)) by Atcsqr.andestech.com with ESMTP id 6911ju5V061971; Thu, 1 Oct 2026 09:45:56 +0800 (+08) (envelope-from cl634@andestech.com) Received: from mail.andestech.com (atcpcs55.andestech.com [10.0.1.155]) by Atcsqr.andestech.com with ESMTPS id 6911jUSF061775 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 1 Oct 2026 09:45:30 +0800 (+08) (envelope-from cl634@andestech.com) Received: from ATCPCS34.andestech.com (10.0.1.134) by atcpcs55.andestech.com (10.0.1.155) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.2.2562.43; Thu, 1 Oct 2026 09:45:30 +0800 Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS34.andestech.com (10.0.1.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Thu, 1 Oct 2026 09:45:30 +0800 From: CL Wang To: Vinod Koul , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley CC: Frank Li , Kees Cook , "Gustavo A . R . Silva" , , , , , , , Conor Dooley Subject: [PATCH v8 1/2] dt-bindings: dmaengine: Add support for ATCDMAC300 DMA engine Date: Thu, 1 Oct 2026 09:45:02 +0800 Message-ID: <20261001014503.786490-2-cl634@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261001014503.786490-1-cl634@andestech.com> References: <20261001014503.786490-1-cl634@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: ATCPCS33.andestech.com (10.0.1.100) To ATCPCS34.andestech.com (10.0.1.134) X-DKIM-Results: atcpcs55.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL:Atcsqr.andestech.com 6911ju5V061971 Document devicetree bindings for Andes ATCDMAC300 DMA engine ATCDMAC300 is the IP name, which is embedded in AndesCore-based platforms or SoCs such as AE350 and Qilai. Signed-off-by: CL Wang Acked-by: Conor Dooley --- Changes for v7: - Rebase onto the current dmaengine/next; no changes from v6 Changes for v6: - Rebase onto dmaengine/next; no changes from v5 Changes for v5: - No changes from v4 Changes for v4: - Use items list format with descriptions for reg property as suggested by Conor Dooley Changes for v3: - Rename DT binding file from andestech,qilai-dma.yaml to andestech,ae350-dma.yaml. - Deprecate IP-core-based compatible usage and align with SoC/platform-based strings. - Dropped Acked-by tag from Conor Dooley due to the above change. --- .../bindings/dma/andestech,ae350-dma.yaml | 67 +++++++++++++++++++ 1 file changed, 67 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/andestech,ae350-dma.yaml diff --git a/Documentation/devicetree/bindings/dma/andestech,ae350-dma.yaml b/Documentation/devicetree/bindings/dma/andestech,ae350-dma.yaml new file mode 100644 index 000000000000..f040a2bf7d4b --- /dev/null +++ b/Documentation/devicetree/bindings/dma/andestech,ae350-dma.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/andestech,ae350-dma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes ATCDMAC300 DMA Controller + +maintainers: + - CL Wang + +allOf: + - $ref: dma-controller.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - andestech,qilai-dma + - const: andestech,ae350-dma + - const: andestech,ae350-dma + + reg: + minItems: 1 + items: + - description: DMA controller register range + - description: cache control in IOCP controller + + reg-names: + minItems: 1 + items: + - const: dma + - const: iocp + + interrupts: + maxItems: 1 + + "#dma-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - "#dma-cells" + +additionalProperties: false + +examples: + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dma-controller@f0c00000 { + compatible = "andestech,ae350-dma"; + reg = <0x0 0xf0c00000 0x0 0x1000>, + <0x0 0xe8000000 0x0 0x10>; + reg-names = "dma", "iocp"; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; + #dma-cells = <1>; + }; + }; +... -- 2.34.1