drivers/clk/imx/clk-frac-pll.c:171:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.

[kernel test robot <lkp@intel.com>]

Hi Thomas,

First bad commit (maybe != root cause):

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   551c722f40809618230001baccf219193e22fc5a
commit: 031cdd3bc3f369553933c1b0f4cb18000162c8ff kunit: Enable PCI on UML without triggering WARN()
date:   1 year, 1 month ago
config: um-randconfig-r2103-20261001 (https://download.01.org/0day-ci/archive/20261001/202610010618.W1vpHMMD-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Fixes: 031cdd3bc3f3 ("kunit: Enable PCI on UML without triggering WARN()")
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202610010618.W1vpHMMD-lkp@intel.com/

cocci warnings: (new ones prefixed by >>)
>> drivers/clk/imx/clk-frac-pll.c:171:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
>> drivers/clk/imx/clk-frac-pll.c:132:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.
   drivers/clk/imx/clk-frac-pll.c:136:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_u64 instead.
--
>> drivers/clk/imx/clk-pfd.c:95:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
--
>> drivers/clk/imx/clk-pfdv2.c:118:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
   drivers/clk/imx/clk-pfdv2.c:177:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
--
>> drivers/clk/imx/clk-pllv2.c:143:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
>> drivers/clk/imx/clk-pllv2.c:100:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_long instead.
--
>> drivers/clk/imx/clk-pllv4.c:111:2-8: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
   drivers/clk/imx/clk-pllv4.c:141:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.
   drivers/clk/imx/clk-pllv4.c:201:1-7: WARNING: do_div() does a 64-by-32 division, please consider using div64_ul instead.

vim +171 drivers/clk/imx/clk-frac-pll.c

6209624b9a5c1e Lucas Stach  2018-12-01  121  
6d50f953f75e76 Brian Masney 2025-07-10  122  static int clk_pll_determine_rate(struct clk_hw *hw,
6d50f953f75e76 Brian Masney 2025-07-10  123  				  struct clk_rate_request *req)
6209624b9a5c1e Lucas Stach  2018-12-01  124  {
6d50f953f75e76 Brian Masney 2025-07-10  125  	u64 parent_rate = req->best_parent_rate;
6209624b9a5c1e Lucas Stach  2018-12-01  126  	u32 divff, divfi;
6209624b9a5c1e Lucas Stach  2018-12-01  127  	u64 temp64;
6209624b9a5c1e Lucas Stach  2018-12-01  128  
6209624b9a5c1e Lucas Stach  2018-12-01  129  	parent_rate *= 8;
6d50f953f75e76 Brian Masney 2025-07-10  130  	req->rate *= 2;
6d50f953f75e76 Brian Masney 2025-07-10  131  	temp64 = req->rate;
6209624b9a5c1e Lucas Stach  2018-12-01 @132  	do_div(temp64, parent_rate);
6209624b9a5c1e Lucas Stach  2018-12-01  133  	divfi = temp64;
6d50f953f75e76 Brian Masney 2025-07-10  134  	temp64 = req->rate - divfi * parent_rate;
6209624b9a5c1e Lucas Stach  2018-12-01  135  	temp64 *= PLL_FRAC_DENOM;
6209624b9a5c1e Lucas Stach  2018-12-01  136  	do_div(temp64, parent_rate);
6209624b9a5c1e Lucas Stach  2018-12-01  137  	divff = temp64;
6209624b9a5c1e Lucas Stach  2018-12-01  138  
6209624b9a5c1e Lucas Stach  2018-12-01  139  	temp64 = parent_rate;
6209624b9a5c1e Lucas Stach  2018-12-01  140  	temp64 *= divff;
6209624b9a5c1e Lucas Stach  2018-12-01  141  	do_div(temp64, PLL_FRAC_DENOM);
6209624b9a5c1e Lucas Stach  2018-12-01  142  
6d50f953f75e76 Brian Masney 2025-07-10  143  	req->rate = parent_rate * divfi + temp64;
6d50f953f75e76 Brian Masney 2025-07-10  144  
6d50f953f75e76 Brian Masney 2025-07-10  145  	req->rate = req->rate / 2;
6209624b9a5c1e Lucas Stach  2018-12-01  146  
6d50f953f75e76 Brian Masney 2025-07-10  147  	return 0;
6209624b9a5c1e Lucas Stach  2018-12-01  148  }
6209624b9a5c1e Lucas Stach  2018-12-01  149  
6209624b9a5c1e Lucas Stach  2018-12-01  150  /*
6209624b9a5c1e Lucas Stach  2018-12-01  151   * To simplify the clock calculation, we can keep the 'PLL_OUTPUT_VAL' at zero
6209624b9a5c1e Lucas Stach  2018-12-01  152   * (means the PLL output will be divided by 2). So the PLL output can use
6209624b9a5c1e Lucas Stach  2018-12-01  153   * the below formula:
6209624b9a5c1e Lucas Stach  2018-12-01  154   * pllout = parent_rate * 8 / 2 * DIVF_VAL;
6209624b9a5c1e Lucas Stach  2018-12-01  155   * where DIVF_VAL = 1 + DIVFI + DIVFF / 2^24.
6209624b9a5c1e Lucas Stach  2018-12-01  156   */
6209624b9a5c1e Lucas Stach  2018-12-01  157  static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
6209624b9a5c1e Lucas Stach  2018-12-01  158  			    unsigned long parent_rate)
6209624b9a5c1e Lucas Stach  2018-12-01  159  {
6209624b9a5c1e Lucas Stach  2018-12-01  160  	struct clk_frac_pll *pll = to_clk_frac_pll(hw);
6209624b9a5c1e Lucas Stach  2018-12-01  161  	u32 val, divfi, divff;
a64a9c088b75cb Abel Vesa    2019-01-18  162  	u64 temp64;
6209624b9a5c1e Lucas Stach  2018-12-01  163  	int ret;
6209624b9a5c1e Lucas Stach  2018-12-01  164  
6209624b9a5c1e Lucas Stach  2018-12-01  165  	parent_rate *= 8;
6209624b9a5c1e Lucas Stach  2018-12-01  166  	rate *= 2;
6209624b9a5c1e Lucas Stach  2018-12-01  167  	divfi = rate / parent_rate;
a64a9c088b75cb Abel Vesa    2019-01-18  168  	temp64 = parent_rate * divfi;
a64a9c088b75cb Abel Vesa    2019-01-18  169  	temp64 = rate - temp64;
6209624b9a5c1e Lucas Stach  2018-12-01  170  	temp64 *= PLL_FRAC_DENOM;
6209624b9a5c1e Lucas Stach  2018-12-01 @171  	do_div(temp64, parent_rate);
6209624b9a5c1e Lucas Stach  2018-12-01  172  	divff = temp64;
6209624b9a5c1e Lucas Stach  2018-12-01  173  
6209624b9a5c1e Lucas Stach  2018-12-01  174  	val = readl_relaxed(pll->base + PLL_CFG1);
6209624b9a5c1e Lucas Stach  2018-12-01  175  	val &= ~(PLL_FRAC_DIV_MASK | PLL_INT_DIV_MASK);
6209624b9a5c1e Lucas Stach  2018-12-01  176  	val |= (divff << 7) | (divfi - 1);
6209624b9a5c1e Lucas Stach  2018-12-01  177  	writel_relaxed(val, pll->base + PLL_CFG1);
6209624b9a5c1e Lucas Stach  2018-12-01  178  
6209624b9a5c1e Lucas Stach  2018-12-01  179  	val = readl_relaxed(pll->base + PLL_CFG0);
6209624b9a5c1e Lucas Stach  2018-12-01  180  	val &= ~0x1f;
6209624b9a5c1e Lucas Stach  2018-12-01  181  	writel_relaxed(val, pll->base + PLL_CFG0);
6209624b9a5c1e Lucas Stach  2018-12-01  182  
6209624b9a5c1e Lucas Stach  2018-12-01  183  	/* Set the NEV_DIV_VAL to reload the DIVFI and DIVFF */
6209624b9a5c1e Lucas Stach  2018-12-01  184  	val = readl_relaxed(pll->base + PLL_CFG0);
6209624b9a5c1e Lucas Stach  2018-12-01  185  	val |= PLL_NEWDIV_VAL;
6209624b9a5c1e Lucas Stach  2018-12-01  186  	writel_relaxed(val, pll->base + PLL_CFG0);
6209624b9a5c1e Lucas Stach  2018-12-01  187  
6209624b9a5c1e Lucas Stach  2018-12-01  188  	ret = clk_wait_ack(pll);
6209624b9a5c1e Lucas Stach  2018-12-01  189  
6209624b9a5c1e Lucas Stach  2018-12-01  190  	/* clear the NEV_DIV_VAL */
6209624b9a5c1e Lucas Stach  2018-12-01  191  	val = readl_relaxed(pll->base + PLL_CFG0);
6209624b9a5c1e Lucas Stach  2018-12-01  192  	val &= ~PLL_NEWDIV_VAL;
6209624b9a5c1e Lucas Stach  2018-12-01  193  	writel_relaxed(val, pll->base + PLL_CFG0);
6209624b9a5c1e Lucas Stach  2018-12-01  194  
6209624b9a5c1e Lucas Stach  2018-12-01  195  	return ret;
6209624b9a5c1e Lucas Stach  2018-12-01  196  }
6209624b9a5c1e Lucas Stach  2018-12-01  197  

:::::: The code at line 171 was first introduced by commit
:::::: 6209624b9a5c1e417b142e9688f5fc96c1e0cd58 clk: imx: Add fractional PLL output clock

:::::: TO: Lucas Stach <l.stach@pengutronix.de>
:::::: CC: Stephen Boyd <sboyd@kernel.org>

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