From: sashiko-bot@kernel.org
To: miquel.raynal@bootlin.com, yamada.masahiro@socionext.com,
vigneshr@ti.com, wenyou.yang@microchip.com,
bbrezillon@kernel.org, "wang wei" <a929244872@163.com>,
richard@nod.at
Cc: linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2] drivers/mtd: rawnand: nandsim: Fix stale NAND_ROW_ADDR_3 with overridesize
Date: Thu, 01 Oct 2026 13:00:35 +0000 [thread overview]
Message-ID: <20261001130036.44E271F000FF@smtp.kernel.org> (raw)
In-Reply-To: <20261001124733.43559-1-a929244872@163.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Medium] mtd: nandsim: address cycle mismatch for 256 MiB / 4096-byte page devices
--
commit d11867536ecbb0d0243c052069d60f5f1a2c4afe
Author: wang wei <a929244872@163.com>
drivers/mtd: rawnand: nandsim: Fix stale NAND_ROW_ADDR_3 with overridesize
The commit fixes a stale NAND_ROW_ADDR_3 flag by re-evaluating it after
changing the size of the simulated device when using the overridesize
parameter. It updates the flag based on the core logic: chip_shift -
page_shift > 16.
> diff --git a/drivers/mtd/nand/raw/nandsim.c b/drivers/mtd/nand/raw/nandsim.c
> index fe968037f75a2..ac82dd7e18a93 100644
> --- a/drivers/mtd/nand/raw/nandsim.c
> +++ b/drivers/mtd/nand/raw/nandsim.c
> @@ -2359,6 +2359,11 @@ static int __init ns_init_module(void)
> targetsize = nanddev_target_size(&chip->base);
> chip->chip_shift = ffs(nsmtd->erasesize) + overridesize - 1;
> chip->pagemask = (targetsize >> chip->page_shift) - 1;
> +
> + if (chip->chip_shift - chip->page_shift > 16)
> + chip->options |= NAND_ROW_ADDR_3;
> + else
> + chip->options &= ~NAND_ROW_ADDR_3;
[Severity: Medium]
Does this logic conflict with the address byte expectation in ns_init()?
For a 256 MiB device with 4096-byte pages, chip_shift - page_shift evaluates
to 28 - 12 = 16. This causes the code here to clear NAND_ROW_ADDR_3, so the
core emits 4 address bytes.
However, ns_init() has hardcoded logic expecting 5 address bytes for devices
larger than 128 MiB:
drivers/mtd/nand/raw/nandsim.c:ns_init() {
...
if (ns->geom.totsz <= (128 << 20)) {
ns->geom.pgaddrbytes = 4;
ns->geom.secaddrbytes = 2;
} else {
ns->geom.pgaddrbytes = 5;
ns->geom.secaddrbytes = 3;
}
...
}
Will this mismatch stall the nandsim state machine and fail operations due to
an address cycle mismatch?
Prior to this change, shrinking a 512 MiB device to 256 MiB left the stale
flag set, which serendipitously matched nandsim's expectation of 5 bytes.
> }
>
> ret = ns_setup_wear_reporting(nsmtd);
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261001124733.43559-1-a929244872@163.com?part=1
prev parent reply other threads:[~2026-10-01 13:00 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-01 12:47 wang wei
2026-10-01 13:00 ` sashiko-bot [this message]
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