From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj2-f13.google.com (mail-pj2-f13.google.com [74.125.227.141]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9E9DD4A92D2 for ; Thu, 1 Oct 2026 13:18:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=74.125.227.141 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790860715; cv=none; b=QNHTTX0Qs6KxF/P5GtGek6hkKHREgwYLo+YUO3JZN+wckOC+Hq9x6t1PPsg0LWFqwqyVfmO5Q78NIhg31bKMxB2XOEuNSK6OEvYNfeVdexGIhvMh58nQR8ojo93P9VIsnV9l33TYgQKv0pfzytt+XFhVTC7uNkVjwioKWApTooA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790860715; c=relaxed/simple; bh=lhRbxtVBIybdQCTOorjTAyoTpO5aS0NzNmk5FzOl1DY=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=UR3Qr0qnGJGgKruu40lSHhAxbbN8FT9f75MAGzDb8JHSRRfJitC+/TleS9dVp9U2VZ8q7k+pKHcoQHP8A+OCgR6VpvVt/4q5STR2mPk765O4TAJTGxfE8zqadxhhICT6uCLRN2Ul77ls7tYI3BjaqBi6ybovR/TI596bCh8VBXk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=JAZZJCxX; arc=none smtp.client-ip=74.125.227.141 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="JAZZJCxX" Received: by mail-pj2-f13.google.com with SMTP id 98e67ed59e1d1-396ccd66bb4so2994064a91.1 for ; Thu, 01 Oct 2026 06:18:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1790860711; x=1791465511; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=g2a/uAq+WStsO8aQx6BMPUzRVm0wlq4SS94ygHqJZbI=; b=JAZZJCxXXUd3ka+O7v4l/WJ4ocLC7Z83gQq9ljIBc64z7owfrmoWQ481IeNJCUy+WL hYC0tQ1Ov60trtWyR47QLr2xOdz3cO6NUH19wI4sWzhbK8ybJxJ72NuDXKGkvzfMGprJ eWv++8/F4nhJzDrYY4OG4G2expb33y/eGPzyyh7S5MwjdLEnMQsMdjs7UmK9FjYyqWx1 dt8iJfQqAFk39BC1fNxr/yQvDdvIqfXGIcHSJesA0d1x1djtQTLPLSQa2btwR4lUOPkn 7RfcapG4poRqgH59687F+1VA42GZV5Ne+DeDVZgxLYqeLNQqWLjO2nJ4YTkBjiz9UxY9 p6mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1790860711; x=1791465511; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=g2a/uAq+WStsO8aQx6BMPUzRVm0wlq4SS94ygHqJZbI=; b=gF79+er7WJ5q8sIBLAesNDlhPP8vAXVqk+fTJlNo43X6mGPuA5x3F3JiuSQeCw8PJf qyf/bkD5V9M6oMRJfdEBXSGifi+OeZNW9Jo81yAM5RapP3Jab0mq3vD2xeekXw2//oJU Aa5QRyrJ9oaltteRGY+m9Ry/QIXOQm/VJjIH5q+rwB4KkrzcbZp4gGGLz46+R3dFM7qX vANNJMy9i31hcubf5D1qFKAuE3aIl9OwibpI9TIF8WaonoaXziUG2jHwYugC4kZTd67L LwmnGO31jFFPDxM3eC6r4bNw7Qva9VXTRbSIrCMQSV26A2r2M5h6ELKYTiVvgntvpMP1 b43g== X-Forwarded-Encrypted: i=1; AKwUvBxgV1o1u9h+/VR4tODp5oBta7PVCgjI3uVCf7tTNp/F6NRYHdtdqCd2vfpeSRm5ZfqfgL7c1I1hUOakIE4=@vger.kernel.org X-Gm-Message-State: AFq9FYJ7/oojMFH9yIXjM4D76YjNQOIUZ/dz/kRyNAZ4bsLUph/I6l4p SQ4Au04JziZzr0h7L7KkPC79qJWvibUJLnJpZ6yFoCGcSd9YGOoafSY+ X-Gm-Gg: AYBFou3ORQbJItKKgG4JU/O7y/3BHaaVcbzXJWKjBPLCzLGMtWRbyeSpqp/EwLN4zB8 x7vwo4z71PXPatq94Yryif6+Ag2gGvO3J2NVd+IY1CWAVcGYTvzEp+kEfk0yg8c/HiseD7yHqee HBF1RMTZIuMqfvL2rm31GPfCRZAS+KkritRK3RHFIvKr1tFbS2B8oFOd77sJWfpYzMWAdH+W1/N R11JHAFajnBLLwp5LyERR/9jC1bOUIw2sFIiGx7IBtmoXyTzM1cOkyWkmruJ0QS3K0hnmc3QaAD U+UtScMxb8bXd04+2ojAuKbpo8AlZ4SWAxKlLOh7579zGbnn3oetqF4i19Sj4pc8OnU6ZCbpvfw SJrWyKDItjC0rrHR458NRKJ0AjeXpdkK66fYn2yF4WLKEKrKJUIPu3wGuEuqYcqQQqT5UCRsGWk QfWibDDUGG+gTzJZ335LCtxCazCwzELeTBqfBhkDVHleCTzOU7dxuMLvBRt69Hfy+Z5kHCX+3So 8A1XKjceRrbmAOmJWAwHkjC05cRXsKOuX6cf9OyekDlu5Pmx6jzOQpz3rBn X-Received: by 2002:a17:90b:5787:b0:3a0:c1de:f720 with SMTP id 98e67ed59e1d1-3a4d197e17emr4062843a91.20.1790860710586; Thu, 01 Oct 2026 06:18:30 -0700 (PDT) Received: from localhost.localdomain (60-250-196-139.hinet-ip.hinet.net. [60.250.196.139]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a4f46bb550sm5016692a91.5.2026.10.01.06.18.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Oct 2026 06:18:29 -0700 (PDT) From: Chi-Wen Weng To: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v2 1/3] spi: dt-bindings: nuvoton,ma35d1-qspi: Add MA35D1 SPI controller Date: Thu, 1 Oct 2026 21:18:16 +0800 Message-Id: <20261001131818.110028-2-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20261001131818.110028-1-cwweng.linux@gmail.com> References: <20261001131818.110028-1-cwweng.linux@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Chi-Wen Weng Extend the existing MA35D1 QSPI binding to also describe the MA35D1 SPI controller. The SPI and QSPI controllers are separate hardware IPs. QSPI additionally supports dual, quad and DTR transfers and a target-mode timeout function, but these differences do not require additional controller-specific Devicetree properties. Both controllers expose the same Devicetree-visible resources and provide up to two native chip-select signals. GPIO chip selects are supported through the generic SPI controller binding. Since the MA35D1 QSPI driver now supports GPIO chip selects, also remove the existing restriction on cs-gpios for the QSPI compatible. Add the nuvoton,ma35d1-spi compatible and update the binding description and examples to cover both controllers. Signed-off-by: Chi-Wen Weng --- .../bindings/spi/nuvoton,ma35d1-qspi.yaml | 41 +++++++++++++++++-- 1 file changed, 37 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml index 40965ec5163b..72f2e1e1219a 100644 --- a/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/nuvoton,ma35d1-qspi.yaml @@ -4,7 +4,17 @@ $id: http://devicetree.org/schemas/spi/nuvoton,ma35d1-qspi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Nuvoton MA35D1 Quad SPI Controller +title: Nuvoton MA35D1 SPI and Quad SPI Controllers + +description: | + The Nuvoton MA35D1 SoC contains separate SPI and QSPI controller IPs. + Both controllers expose the same Devicetree-visible resources and provide + two native chip-select signals. GPIO chip selects are supported through the + generic SPI controller binding. + + The QSPI controller additionally supports dual, quad and DTR transfers and + a target-mode timeout function. These capability differences do not require + additional controller properties. maintainers: - Chi-Wen Weng @@ -14,7 +24,9 @@ allOf: properties: compatible: - const: nuvoton,ma35d1-qspi + enum: + - nuvoton,ma35d1-spi + - nuvoton,ma35d1-qspi reg: maxItems: 1 @@ -33,8 +45,6 @@ properties: maximum: 2 default: 2 - cs-gpios: false - required: - compatible - reg @@ -59,7 +69,30 @@ examples: interrupts = ; clocks = <&clk QSPI0_GATE>; resets = <&sys MA35D1_RESET_QSPI0>; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + spi@40600000 { + compatible = "nuvoton,ma35d1-spi"; + reg = <0 0x40600000 0 0x10000>; + interrupts = ; + clocks = <&clk SPI0_GATE>; + resets = <&sys MA35D1_RESET_SPI0>; + #address-cells = <1>; #size-cells = <0>; }; }; +... -- 2.25.1