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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: k7wA583/+GXsWrfYiRaB3m5PL4HuXG1GXpYjBCMKE6uGmpH1Sw7uXK1bBLzzgZJMuOtSkd1VFyAb16F6pvQayv7FAkbTgtxzhPeyUvwrVlHSo+D+cNmUrJ5l6bCPbvtLlfdAVD266ZGfqYkYDRgmWhYs7yzDz0vgaP2iEC09UoK96ORncz4uYh/mr7/8EVHg8RDemvHFecVx+9SJSfiP1ItrYlrsJMTUayKjgGko0+yYo7EVmQ80pTxCKLnWTUrKRjcfuZfIIyRVznePLfspRnYKPhRMaPbYgDMIbI7fukpAYJlyVV139+eVwcnMq2265HtxKUPxbx7XYTaxJ/1N6X7GIsfCZVlmrtU/pz/+c8dIhT/Nx+0oTqaOgskgQ93puNVSpYak6pyMzCrfU/KY6G5K1p6aJD1sEkTqwXkFq2UuEzK/T5jKlAH2stRZsEWE X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Oct 2026 19:30:55.0216 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6672af75-a0d1-4e28-5baa-08df1ff28308 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E65.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR12MB4438 Configure the sparsebitmask (sbm) topology for multi-node processors once SRAT is parsed and cpu_to_node() mappings are stable. Former commit enabled parsing node mappings for disabled CPUs during SRAT parsing and every CPU will have a valid mapping before the sbm topology parsing is attempted ensuring correct bounds for max_threads_per_instance. XXX: If _PXM mappings cannot be trusted for disabled CPUs, an alternate logic needs to be added. See PowerPC enablement later in the series. Signed-off-by: K Prateek Nayak --- Only build tested with config from https://lore.kernel.org/lkml/202609190905.OZTcO07l-lkp@intel.com/ --- arch/loongarch/kernel/smp.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c index d4b5d1b6bb01..d8155b26c4df 100644 --- a/arch/loongarch/kernel/smp.c +++ b/arch/loongarch/kernel/smp.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -73,6 +74,10 @@ static cpumask_t cpu_llc_shared_setup_map; /* representing cpus for which core maps can be computed */ static cpumask_t cpu_core_setup_map; +/* sbm setup data - only needed during init */ +static cpumask_t cpu_sbm_setup_map __initdata; +static int __node_thread_count[NR_CPUS] __initdata; + struct secondary_data cpuboot_data; static DEFINE_PER_CPU(int, cpu_state); @@ -362,10 +367,16 @@ void __init loongson_smp_setup(void) pr_info("Detected %i available CPU(s)\n", loongson_sysconf.nr_cpus); } +int arch_sbm_cpu_instance_id(int cpu) +{ + return cpu_to_node(cpu); +} + void __init loongson_prepare_cpus(unsigned int max_cpus) { int i = 0; int threads_per_core = 0; + int num_sbm_instances, max_threads_per_instance = 1; parse_acpi_topology(); cpu_data[0].global_id = cpu_logical_map(0); @@ -388,6 +399,31 @@ void __init loongson_prepare_cpus(unsigned int max_cpus) per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; cpu_smt_set_num_threads(threads_per_core, threads_per_core); + + for_each_possible_cpu(i) { + bool found = false; + int j; + + for_each_cpu(j, &cpu_sbm_setup_map) { + if (cpu_to_node(i) == cpu_to_node(j)) { + found = true; + break; + } + } + + if (!found) { + cpumask_set_cpu(i, &cpu_sbm_setup_map); + __node_thread_count[i] = 1; + continue; + } + + __node_thread_count[j] += 1; + max_threads_per_instance = max(max_threads_per_instance, + __node_thread_count[j]); + } + + num_sbm_instances = cpumask_weight(&cpu_sbm_setup_map); + sbm_set_topology(num_sbm_instances, max_threads_per_instance); } /* -- 2.34.1