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AKwUvBwWuwO/+vpkd85k5fBLlX1+3SR4EXEFE4AhAGnZUl/CI7IokH497Iv/FfIRSP8Va6swEkWwLcl3r1BZvbc=@vger.kernel.org X-Gm-Message-State: AFuF++l1wkle0/KPJAht5TDJg6WyxI/+b5bLBbYu4pyl5+1IUYBvyOHE 471mKP5K1d+oUSZQpotlJuA6LJEb1xSF2fDamHw6gfVqhzy3BBUjHkBKDW3osKqchJ6uk+h80eX 7mMnvg3nKLILwW5aY1BjEBafmKw== X-Received: from ilbcx6.prod.google.com ([2002:a05:6e02:3c06:b0:50d:b50e:1675]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6808:1211:b0:4b9:a829:f015 with SMTP id 5614622812f47-4f529d297bemr430489b6e.33.1790890437780; Thu, 01 Oct 2026 14:33:57 -0700 (PDT) Date: Thu, 1 Oct 2026 21:33:55 +0000 In-Reply-To: <8e47bb89-a894-4fd0-9f96-e11b5dea1972@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260924172928.2110956-1-coltonlewis@google.com> <8e47bb89-a894-4fd0-9f96-e11b5dea1972@linaro.org> X-Mailer: git-send-email 2.56.0.rc1.315.gc6ed9934b7-goog Message-ID: <20261001213357.2088894-1-coltonlewis@google.com> Subject: Re: [PATCH v9 00/22] ARM64 PMU Partitioning From: Colton Lewis To: James Clark Cc: Colton Lewis , Marc Zyngier , Oliver Upton , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Fuad Tabba , Catalin Marinas , Will Deacon , Mark Rutland , Paolo Bonzini , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Robin Murphy , Zide Chen , Alexandru Elisei , Ganapatrao Kulkarni , Mingwei Zhang , Jonathan Corbet , Russell King , Shuah Khan , linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="UTF-8" Hi James, On Wed, Sep 30, 2026 at 04:25:36PM +0100, James Clark wrote: > Looks good to me, everything seems to be working now: > > Tested-by: James Clark Thank you for testing and for all the reviews! > There are still a few Sashiko comments though, and one critical one about > racing with pseudo-NMI PMU interrupts that looked reasonable. I tried to > test it and reproduce an actual issue but couldn't, so maybe it's bogus. The "Critical" Sashiko comment on Patch 19/22 (claiming that clearing hardware PMOVSSET_EL0 loses overflow bits because the guest has direct untrapped access to PMOVSSET_EL0) is a false positive: Patch 09/22 sets HDFGRTR_EL2_PMOVS and HDFGWTR_EL2_PMOVS (and without FGT, MDCR_EL2.TPM is set), so guest accesses to PMOVSSET_EL0 and PMOVSCLR_EL0 always trap to pmu_reg_read() / pmu_reg_write(). The pseudo-NMI race comments on Patch 11/22 and Patch 19/22 are theoretically possible in a narrow 2-instruction RMW window because local_irq_save() does not mask GICv3 pseudo-NMIs, which explains why it wasn't reproducible in practice. In v10 I will make the PMOVSSET_EL0 shadow updates and vcpu->arch.mdcr_el2 assignment atomic, and address the other valid Sashiko findings. Thanks, Colton