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The next display on that CTL then waits for a flush which can't complete. On SDA660, going back to fbcon from a two-mixer mode leaves the LM_1 bit pending, and every following frame of the single-mixer mode times out: [dpu error]vblank timeout: 80 [dpu error]wait for commit done returned -110 Only trigger the flush from the teardown on DPU >= 5.0. The legacy CTL gets its registers flushed by its next user, as downstream does, which rewrites CTL_TOP without a flush when it stops a CTL. Fixes: 22cb02bc96ff ("drm/msm/disp/dpu: reset the datapath after timing engine disable") Assisted-by: LLM Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1f20695f81e3..5a06a0fbc7e1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2339,8 +2339,11 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) if (ctl->ops.reset_intf_cfg) ctl->ops.reset_intf_cfg(ctl, &intf_cfg); - ctl->ops.trigger_flush(ctl); - ctl->ops.trigger_start(ctl); + /* a legacy CTL latches its flush at the vsync of a stopped interface */ + if (phys_enc->dpu_kms->catalog->mdss_ver->core_major_ver >= 5) { + ctl->ops.trigger_flush(ctl); + ctl->ops.trigger_start(ctl); + } ctl->ops.clear_pending_flush(ctl); } --- base-commit: 5e4a3f7b262060d70cfdc7889cfe0f4aba9ea3fc change-id: 20261002-encoder-flush-old-ctl-45d4bbb489d8 Best regards, -- With best wishes Dmitry