[RFC PATCH 1/1] usb: dwc3: Clear SUSPHY before issuing core soft reset

[Elson Serrao <elson.serrao@oss.qualcomm.com>]

The controller clears DCTL.CSFTRST only after all required logic has
been reset and all PHY clocks are active. If SUSPHY remains set, the PHY
may not be fully active during the reset sequence, causing the core soft
reset to fail to complete.
 
Clear SUSPHY before asserting DCTL.CSFTRST to ensure the PHY remains
active while the reset is in progress.

Fixes: cc5bfc4e16fc ("usb: dwc3: Set SUSPENDENABLE soon after phy init")
Signed-off-by: Elson Serrao <elson.serrao@oss.qualcomm.com>
---
 drivers/usb/dwc3/core.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index fd5c2cd36c59..282a853c364e 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -332,6 +332,13 @@ int dwc3_core_soft_reset(struct dwc3 *dwc)
 	if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 		return 0;
 
+	/*
+	 * The core clears DCTL.CSFTRST only after all necessary logic is
+	 * reset and all PHY clocks are active/running. Clear SUSPHY before
+	 * issuing the reset so that the PHY is active.
+	 */
+	dwc3_enable_susphy(dwc, false);
+
 	reg = dwc3_readl(dwc, DWC3_DCTL);
 	reg |= DWC3_DCTL_CSFTRST;
 	reg &= ~DWC3_DCTL_RUN_STOP;
-- 
2.34.1