From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9927A4334AD; Fri, 2 Oct 2026 07:44:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790927074; cv=none; b=I5QnlsoWNmkaT466R/OVj2Qo533POgoIQRyn8/5POzWjZbPWiyt8ZkNGGkhVAGoz6KahuUc2UdpmvWMPUdIfCYJa1QmkoCLgXVuZ9Zj5zVOHkBUwzDssJNxWLnAsfzi5hgMyRM7D4Nk/S9/q9N86Lf0E9aO9T+Zq0glAgGKtsRk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790927074; c=relaxed/simple; bh=sPbYMfvbF8KEqGaf78EfrsdNbcTrPn/qbh33aXQCook=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version:Content-Type; b=vAK7aESPg6atOrWfB12U5pixFZKkWufVG9/wFM8lIt5rcrjDBg1741JJFe0tcpaoDEOHmjLErRUK6PSDIWHgsNRLaT3F/bVQf+GMZOxE9/MwNq3uqhJaktXNhdYhu/NEKemAvpymP9Vp3+l+FLYqubkh2a76dD41b0+415Rnaww= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=jRVYFUK5; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="jRVYFUK5" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6927hlqF73646795, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1790927027; bh=g2nQCEM3gDeJGvqRr7JC/m2BFU1UygahQMSW9jrruUQ=; h=From:To:CC:Subject:Date:Message-ID:MIME-Version: Content-Transfer-Encoding:Content-Type; b=jRVYFUK5YnoRmiNDeKklzZ1pdgInsSTd9LlydFTjxUV5OrE/HYOAnw2MLeTp8PncV tFvJt3/CO+lLhssxlnVZWvaL29a1KffXYQVOsG9HkLzynokJeqILy5s5YbVi7wcdya 9ejE0ogtij8iq1ZBreAnB75V/B0sCnLu2/+e/+PfxJq73g2YndDyv/5lQUGGt7kJGJ hCxqHMZGe1Smk+/zWye7PrNAttAqySW04bbbLegGNAjNXSBnBqhjNWTzFmZbgg7oR9 b2gwpm3FPsNRjZt1D4kjdYBVCC7EvJ67rV0RbX3ntd/QSc1O2G3NKOnf9poR6xB+9c RruxXEJatF9Pg== Received: from mail.realtek.com (rtkexhmbs02.realtek.com.tw[172.21.6.41]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 6927hlqF73646795 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 Oct 2026 15:43:47 +0800 Received: from RTKEXHMBS01.realtek.com.tw (172.21.6.40) by RTKEXHMBS02.realtek.com.tw (172.21.6.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Fri, 2 Oct 2026 15:43:46 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS01.realtek.com.tw (172.21.6.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Fri, 2 Oct 2026 15:43:31 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Fri, 2 Oct 2026 15:43:31 +0800 From: Yu-Chun Lin To: , , , , , , , , , CC: , , , , , , , , Subject: [PATCH v15 00/11] clk / reset: realtek: Add RTD1625 clock and reset support Date: Fri, 2 Oct 2026 15:43:20 +0800 Message-ID: <20261002074331.3066919-1-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Hello, This patch series adds the clock and reset controller support for Realtek's RTD1625 SoC platform. Because the reset controllers share the same register space with the clock controllers on this platform, we utilize the Auxiliary Bus framework to decouple them. The clock controllers act as the primary devices, registering the reset controllers as auxiliary devices. To make it easier for maintainers to review, the series has been organized by subsystem: 1. Device Tree Bindings: - Add bindings for the Realtek RTD1625 Clock & Reset Controllers. 2. Reset Subsystem: - Introduce the basic Realtek reset infrastructure. - Add the RTD1625-CRT and RTD1625-ISO platform reset drivers. 3. Clock Subsystem Infrastructure: - Introduce a common probe, and add support for basic clocks including PLLs, gate clocks, mux clocks, and MMC-tuned PLLs. 4. Clock Platform Drivers: - Add the clock controller drivers for RTD1625-CRT and RTD1625-ISO. - These drivers provide the clock sources and instantiate the corresponding auxiliary reset devices. Best regards, Yu-Chun Lin --- Changes in v15: Patch 1 : - Add macros for RTD1625_CRT_PLL_VODMA and RTD1625_CRT_CLK_DDSA_DIV4. Patch 4: - Remove reset-related configurations. - Switch the registration order of clock and reset controllers. Patch 6: - Improve commit message and add inline comments for the write-enable mechanism. - Add common helpers 'rtk_clk_regmap_gate_enable()' and 'rtk_clk_regmap_gate_disable()'. Patch 7: - Simplify 'rtk_clk_regmap_mux_get_parent()' to return the result directly. Patch 9 & 10: - Assign parents to gate clocks. - Add a read-only hardware PLL 'pll_vodma' and a fixed-factor clock 'clk_ddsa_div4'. v14: https://lore.kernel.org/lkml/20260901072446.2563145-1-eleanor.lin@realtek.com/ v13: https://lore.kernel.org/lkml/20260812020009.3480538-1-eleanor.lin@realtek.com/ v12: https://lore.kernel.org/lkml/20260804163807.1285869-1-eleanor.lin@realtek.com/ v11: https://lore.kernel.org/lkml/20260728142806.1954638-1-eleanor.lin@realtek.com/ v10: https://lore.kernel.org/lkml/20260713155630.3054636-1-eleanor.lin@realtek.com/ v9: https://lore.kernel.org/lkml/20260624112940.3475605-1-eleanor.lin@realtek.com/ v8: https://lore.kernel.org/lkml/20260610080824.255063-1-eleanor.lin@realtek.com/ v7: https://lore.kernel.org/lkml/20260508111641.3192177-1-eleanor.lin@realtek.com/ v6: https://lore.kernel.org/lkml/20260402073957.2742459-1-eleanor.lin@realtek.com/ v5: https://lore.kernel.org/lkml/20260324025332.3416977-1-eleanor.lin@realtek.com/ v4: https://lore.kernel.org/lkml/20260313081100.596224-1-eleanor.lin@realtek.com/ v3: https://lore.kernel.org/lkml/20260122110857.12995-1-eleanor.lin@realtek.com/ v2: https://lore.kernel.org/lkml/20260113112333.821-1-eleanor.lin@realtek.com/ v1: https://lore.kernel.org/lkml/20251229075313.27254-1-eleanor.lin@realtek.com/ Cheng-Yu Lee (9): reset: Add Realtek basic reset support reset: realtek: Add RTD1625 reset controller driver clk: realtek: Introduce common probe() clk: realtek: Add support for phase locked loops (PLLs) clk: realtek: Add support for gate clock clk: realtek: Add support for mux clock clk: realtek: Add support for MMC-tuned PLL clocks clk: realtek: Add RTD1625-CRT clock controller driver clk: realtek: Add RTD1625-ISO clock controller driver Yu-Chun Lin (2): dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller arm64: dts: realtek: Add clock support for RTD1625 .../bindings/clock/realtek,rtd1625-clk.yaml | 58 ++ MAINTAINERS | 10 + arch/arm64/boot/dts/realtek/kent.dtsi | 33 + drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/realtek/Kconfig | 45 + drivers/clk/realtek/Makefile | 12 + drivers/clk/realtek/clk-pll-mmc.c | 430 +++++++++ drivers/clk/realtek/clk-pll.c | 217 +++++ drivers/clk/realtek/clk-pll.h | 60 ++ drivers/clk/realtek/clk-regmap-gate.c | 64 ++ drivers/clk/realtek/clk-regmap-gate.h | 65 ++ drivers/clk/realtek/clk-regmap-mux.c | 38 + drivers/clk/realtek/clk-regmap-mux.h | 43 + drivers/clk/realtek/clk-rtd1625-crt.c | 822 ++++++++++++++++++ drivers/clk/realtek/clk-rtd1625-iso.c | 140 +++ drivers/clk/realtek/clk-rtk-common.c | 84 ++ drivers/clk/realtek/clk-rtk-common.h | 37 + drivers/clk/realtek/freq_table.c | 57 ++ drivers/clk/realtek/freq_table.h | 22 + drivers/reset/Kconfig | 1 + drivers/reset/Makefile | 1 + drivers/reset/realtek/Kconfig | 19 + drivers/reset/realtek/Makefile | 3 + drivers/reset/realtek/reset-rtd1625.c | 262 ++++++ drivers/reset/realtek/reset-rtk-common.c | 73 ++ drivers/reset/realtek/reset-rtk-common.h | 29 + .../dt-bindings/clock/realtek,rtd1625-clk.h | 166 ++++ include/dt-bindings/reset/realtek,rtd1625.h | 171 ++++ 29 files changed, 2964 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/realtek,rtd1625-clk.yaml create mode 100644 drivers/clk/realtek/Kconfig create mode 100644 drivers/clk/realtek/Makefile create mode 100644 drivers/clk/realtek/clk-pll-mmc.c create mode 100644 drivers/clk/realtek/clk-pll.c create mode 100644 drivers/clk/realtek/clk-pll.h create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h create mode 100644 drivers/clk/realtek/clk-regmap-mux.c create mode 100644 drivers/clk/realtek/clk-regmap-mux.h create mode 100644 drivers/clk/realtek/clk-rtd1625-crt.c create mode 100644 drivers/clk/realtek/clk-rtd1625-iso.c create mode 100644 drivers/clk/realtek/clk-rtk-common.c create mode 100644 drivers/clk/realtek/clk-rtk-common.h create mode 100644 drivers/clk/realtek/freq_table.c create mode 100644 drivers/clk/realtek/freq_table.h create mode 100644 drivers/reset/realtek/Kconfig create mode 100644 drivers/reset/realtek/Makefile create mode 100644 drivers/reset/realtek/reset-rtd1625.c create mode 100644 drivers/reset/realtek/reset-rtk-common.c create mode 100644 drivers/reset/realtek/reset-rtk-common.h create mode 100644 include/dt-bindings/clock/realtek,rtd1625-clk.h create mode 100644 include/dt-bindings/reset/realtek,rtd1625.h -- 2.43.0