From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from rtits2.realtek.com.tw (rtits2.realtek.com [211.75.126.72]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0A5B439014; Fri, 2 Oct 2026 07:44:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=211.75.126.72 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790927074; cv=none; b=J14Y+y3E79Ivk1lf4tP616fSDPM3yjIZDW0ZIlGfIYo3eHKm+74qIpcIcpbwS9FQiOoa2/eyh1pfGrG9gB0CXg4yLsKbjE+R7Tqz6SNZQYLoDeXiIiIQglyMemAgBs72YxIoBB2YptMV4L3oQK9Fvvqw99F3V1KQvUaMJl3L6lo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1790927074; c=relaxed/simple; bh=hg420Rr6H1ksxlMrLe8t5nxWSkbnMZfi0IvptrTqshE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=TTGw3+slMDxLSaYj3isVSeGeO1nHTw308x5TkovJbNjKGi8/ucu6+oIvbPwAGfxlrpsCOYWNg+Z9x//j0ZNA+jcZguRY3RMQl1oY/0N0AEwW0Rhee+bhTpkot5LaT6wFHVsps+UUR86Gybh7wKYvOz69m+WnyEdRSC7N5hYW/wA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com; spf=pass smtp.mailfrom=realtek.com; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b=t5CsgNYo; arc=none smtp.client-ip=211.75.126.72 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=realtek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=realtek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=realtek.com header.i=@realtek.com header.b="t5CsgNYo" X-SpamFilter-By: ArmorX SpamTrap 5.80 with qID 6927hmnzF3646810, This message is accepted by code: ctloc85258 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=realtek.com; s=dkim; t=1790927028; bh=0eM6Na08tEd3wLZK59YfCDCjW7j4FfA47GQOHkh3kYg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Transfer-Encoding:Content-Type; b=t5CsgNYoZfgN98XO90L37tL/zxcaAxY223xqc0QTDOFI4a2hlsaU8IFmglNAm/sWj yIPQWufGZdzlCTOHBCOVzir+TzI/CvxRATAougYIcLCD+ROgW9e33i5Xmbn/x8buMg 4G3sKg8MoIU5c3Joa25JbvGUp+5Ymr8NXxqqd77oYuft58uu/dgp07q8t+JAAAXU6z kUF85mwhS2SypICG4LZZGIUNE0gM4PFv865GPOy8CcWWOfJIolmOWxoIm35EVoYgBd KKYQ4xgeABag8MB0ZtbPJS/VoTfbq/GBbJrqh3STvsn/2GFLtkkAqQabtlqILXU0rD Gr4fMvrZxNmFw== Received: from mail.realtek.com (rtkexhmbs03.realtek.com.tw[10.21.1.53]) by rtits2.realtek.com.tw (8.15.2/3.29/5.94) with ESMTPS id 6927hmnzF3646810 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 Oct 2026 15:43:48 +0800 Received: from RTKEXHMBS06.realtek.com.tw (10.21.1.56) by RTKEXHMBS03.realtek.com.tw (10.21.1.53) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Fri, 2 Oct 2026 15:43:33 +0800 Received: from cn1dhc-k02 (172.21.252.101) by RTKEXHMBS06.realtek.com.tw (10.21.1.56) with Microsoft SMTP Server id 15.2.2562.49 via Frontend Transport; Fri, 2 Oct 2026 15:43:33 +0800 From: Yu-Chun Lin To: , , , , , , , , , CC: , , , , , , , , , Brian Masney Subject: [PATCH v15 06/11] clk: realtek: Add support for gate clock Date: Fri, 2 Oct 2026 15:43:26 +0800 Message-ID: <20261002074331.3066919-7-eleanor.lin@realtek.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20261002074331.3066919-1-eleanor.lin@realtek.com> References: <20261002074331.3066919-1-eleanor.lin@realtek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain From: Cheng-Yu Lee Introduce clk_regmap_gate_ops supporting enable, disable, and is_enabled for standard regmap gate clocks. To accommodate hardware designs, the enable and disable operations handle a 'write_en' flag, which asserts an adjacent write-enable bit (bit_idx + 1) simultaneously when modifying the gate bit. Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled. Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin Reviewed-by: Brian Masney --- Changes in v15: - Improve commit message and add inline comments for the write-enable mechanism. - Add common helpers 'rtk_clk_regmap_gate_enable()' and 'rtk_clk_regmap_gate_disable()'. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-regmap-gate.c | 64 ++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-gate.h | 65 +++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 71edc18121c6..840aff067b61 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += clk-rtk-common.o clk-rtk-y += clk-pll.o +clk-rtk-y += clk-regmap-gate.o clk-rtk-y += freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/clk-regmap-gate.c new file mode 100644 index 000000000000..7033aeb1cd82 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.c @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include +#include "clk-regmap-gate.h" + +static int rtk_clk_regmap_gate_update(struct clk_hw *hw, bool enable) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + unsigned int mask = BIT(clkg->bit_idx); + unsigned int val = enable ? mask : 0; + + /* + * Hardware specific design: to modify the gate bit, the adjacent + * write-enable bit (bit_idx + 1) must be asserted simultaneously. + */ + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static int rtk_clk_regmap_gate_enable(struct clk_hw *hw) +{ + return rtk_clk_regmap_gate_update(hw, true); +} + +static void rtk_clk_regmap_gate_disable(struct clk_hw *hw) +{ + rtk_clk_regmap_gate_update(hw, false); +} + +static int rtk_clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + int ret; + u32 val; + + ret = regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val); + if (ret < 0) + return ret; + + return !!(val & BIT(clkg->bit_idx)); +} + +const struct clk_ops rtk_clk_regmap_gate_ops = { + .enable = rtk_clk_regmap_gate_enable, + .disable = rtk_clk_regmap_gate_disable, + .is_enabled = rtk_clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ops, "CLK_REALTEK"); + +const struct clk_ops rtk_clk_regmap_gate_ro_ops = { + .is_enabled = rtk_clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ro_ops, "CLK_REALTEK"); diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/clk-regmap-gate.h new file mode 100644 index 000000000000..9303adda3166 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H +#define __CLK_REALTEK_CLK_REGMAP_GATE_H + +#include "clk-rtk-common.h" + +struct rtk_clk_regmap_gate { + struct rtk_clk_regmap clkr; + unsigned int gate_ofs; + u8 bit_idx; + u32 write_en : 1; +}; + +#define __rtk_clk_regmap_gate_hw(_p) __rtk_clk_regmap_hw(&(_p)->clkr) + +#define __RTK_CLK_REGMAP_GATE(_name, _parent, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct rtk_clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT(#_name, _parent, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define RTK_CLK_REGMAP_GATE(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define RTK_CLK_REGMAP_GATE_RO(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +#define __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct rtk_clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT_NO_PARENT(#_name, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define RTK_CLK_REGMAP_GATE_NO_PARENT(_name, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define RTK_CLK_REGMAP_GATE_NO_PARENT_RO(_name, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +static inline struct rtk_clk_regmap_gate *to_rtk_clk_regmap_gate(struct clk_hw *hw) +{ + struct rtk_clk_regmap *clkr = to_rtk_clk_regmap(hw); + + return container_of(clkr, struct rtk_clk_regmap_gate, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_gate_ops; +extern const struct clk_ops rtk_clk_regmap_gate_ro_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */ -- 2.43.0