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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH1PEPF0000AD7C.mail.protection.outlook.com (10.167.244.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Fri, 2 Oct 2026 11:33:21 +0000 Received: from airavat.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Fri, 2 Oct 2026 06:33:18 -0500 From: Vishal Badole To: , , , , CC: Vishal Badole Subject: [PATCH v3 0/2] EDAC/amd64: Fix UMC csrow decode and consolidate Family 1Ah setup Date: Fri, 2 Oct 2026 17:02:02 +0530 Message-ID: <20261002113204.3358815-1-Vishal.Badole@amd.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7C:EE_|DS0PR12MB999290:EE_ X-MS-Office365-Filtering-Correlation-Id: a4ff1286-edde-46c0-21ed-08df2078f663 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|82310400026|376014|36860700016|18002099003|13003099007|56012099006|11063799006|10067099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VOCJwUuAAoXkTQMJpMLtJV79LrackdMaulv35wJ5Za7BFapnXYBd0q+0+tA0Wl+7CTw2DuXBWxyxZjEqcSmvQH8kwLSsQq8+55KxfZKARpcNpqpLQXS2d+4tUTHSOTu52+HGV3EKINrQuAmAv8xCh/5TVj5N2YraSIzCCTMGHh8OK/tojSus0IxvWLt8SCREn2Vk1pyCkrnszOzRH/hTr7Rojo9hFu4VcwI4LrXahheWlzxI2jO+zL6VGyuXzPF0gq9CqNxrwoqivRAYAkUF6i+ptmUbodavv18B9J9dBuC5ow4uEZf3WYPC5XTRjdzys38yo4KK9BRTkQ+sP7KaFt9s42ZdK9QDG7gw96CaXlFt7CPUX8sLM+u0zocCuE1zh20NNLuJZNX6CGh493iUB6F9f/1Ji+DwVKJ/igHv1xRPz0XeT1wUca9A7DlzWDOg X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Oct 2026 11:33:21.1218 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4ff1286-edde-46c0-21ed-08df2078f663 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB999290 Two small amd64_edac fixes/cleanups for AMD Family 1Ah. Patch 1 is the fix: mask the UMC chip select with 0x3, not 0x7. Only four chip selects exist, so the old mask could decode an out-of-range csrow and trip an EDAC warning. Patch 2 sets zn_regs_v2 once at the Family 1Ah level instead of in each model case, so future models cannot miss the v2 register layout. Changes since v2: - Patch 1 (fix): Simplified the commit message and updated the code comment. Changes since v1: - Patch 1 (fix): Added Fixes: and Cc: stable, and move the fix first. - Patch 2 (cleanup): Updated the commit message. v2: https://lore.kernel.org/all/20260928180935.472319-1-Vishal.Badole@amd.com/ v1: https://lore.kernel.org/all/20260925172639.97063-1-Vishal.Badole@amd.com/ Vishal Badole (2): EDAC/amd64: Mask UMC chip select to the four implemented selects EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models drivers/edac/amd64_edac.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) -- 2.34.1