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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by CH1PEPF0000AD7C.mail.protection.outlook.com (10.167.244.84) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.472.14 via Frontend Transport; Fri, 2 Oct 2026 11:33:26 +0000 Received: from airavat.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Fri, 2 Oct 2026 06:33:22 -0500 From: Vishal Badole To: , , , , CC: Vishal Badole Subject: [PATCH v3 2/2] EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models Date: Fri, 2 Oct 2026 17:02:04 +0530 Message-ID: <20261002113204.3358815-3-Vishal.Badole@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20261002113204.3358815-1-Vishal.Badole@amd.com> References: <20261002113204.3358815-1-Vishal.Badole@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH1PEPF0000AD7C:EE_|SN7PR12MB7323:EE_ X-MS-Office365-Filtering-Correlation-Id: 87d8b5a8-d757-46dd-5fe0-08df2078f9d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|376014|1800799024|82310400026|11063799006|56012099006|10067099003|18002099003|22082099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: NRSMeW89F32scxnW6pZuikoUZDcb+JdB0NMeEgCAMGSC9iZaUdf51Qdqe3ULdacu0HIMGRpY236helKdrt78KgTjXvllwCbNfDXxHcoHcWsl11DKXSM2XnXKPzQ8drj3SIxIHBCQZ0gQVoijEsIhYyrCLbo4lQHkZ6yG6A9UisLL82hfhgFwDwe7/Tvagwf+Y3g/9CLwMuQ7lCZCmEat9FRZ0+MXpZJgwBQ0/EDgKnp45y9hQvLrUaxK37tw5jd0s8B9Wtjf8A/sTVIJQM4c+4VxVLHA0f5fKh+dS/wt9QH5n9Mf4CGssmxeUSIbncJQBIN2aPZ1WdD6EJe1FFBRhqnZCpJMQj3jdiPqFkdUFdQMITrV9h+ml4cSNYheVVpAmi4dc6oCskfgGK4/dxrjCZ0TklnwLU2TmNyLjqYkJ1NEtuZ8hCyoilVek2ORmGZE X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Oct 2026 11:33:26.8967 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 87d8b5a8-d757-46dd-5fe0-08df2078f9d4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CH1PEPF0000AD7C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7323 All Family 1Ah models use the v2 register layout. Today zn_regs_v2 is set in each model case. This works, but a new model could forget to set it and read the UMC registers at the wrong offsets. Set zn_regs_v2 once at the Family 1Ah level so it applies to all models uniformly, and drop the per-model assignments. No functional change intended. Suggested-by: Yazen Ghannam Signed-off-by: Vishal Badole Reviewed-by: Yazen Ghannam --- drivers/edac/amd64_edac.c | 8 ++------ 1 file changed, 2 insertions(+), 6 deletions(-) diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c index 0c0d11c72925..708fc1b4a999 100644 --- a/drivers/edac/amd64_edac.c +++ b/drivers/edac/amd64_edac.c @@ -3887,23 +3887,19 @@ static int per_family_init(struct amd64_pvt *pvt) break; case 0x1A: + pvt->flags.zn_regs_v2 = 1; + switch (pvt->model) { case 0x00 ... 0x1f: pvt->max_mcs = 12; - pvt->flags.zn_regs_v2 = 1; - break; - case 0x40 ... 0x4f: - pvt->flags.zn_regs_v2 = 1; break; case 0x50 ... 0x57: case 0xc0 ... 0xc7: pvt->max_mcs = 16; - pvt->flags.zn_regs_v2 = 1; break; case 0x90 ... 0x9f: case 0xa0 ... 0xaf: pvt->max_mcs = 8; - pvt->flags.zn_regs_v2 = 1; break; } break; -- 2.34.1