[PATCH] arm64: dts: qcom: qcs6490-rb3gen2: add endpoint buses

[Alex Elder <elder@riscstar.com>]

The TC9564 SoC incorporates a PCIe switch, which is connected via
the second PCI segment (0001) on the RB3gen2 platform.  The third
downstream port of that switch (pcie@3,0) has an embedded PCIe
endpoint that implements two PCIe functions.  The SoC implements
other peripherals, and they will be accessed via PCI endpoint bus.

Record the PCI VID/PID compatible string for the embedded PCI functions
attached to the third downstream switch port.  Define the pci-ep-bus
sub-nodes for each, along with the #address-cells, #size-cells, and
ranges properties for both the endpoint and its pci-ep-bus node.

For PCI endpoint bus, a PCI function's ranges property will be updated
dynamically to incorporate the address ranges assigned to each BAR
during PCI enumeration.

Co-developed-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Daniel Thompson <daniel@riscstar.com>
Signed-off-by: Alex Elder <elder@riscstar.com>
---

			===== PLEASE NOTE =====

A version of this patch was previously included in this series:
  https://lore.kernel.org/lkml/20260918152659.413268-1-elder@riscstar.com/
The first two patches in that series are now in char-misc-next

This patch must go through the Qualcomm tree.  However for this to
function correctly, it depends on this code getting merged:
  https://lore.kernel.org/lkml/20260924222444.1351466-1-elder@riscstar.com/

I sent this message today to clear up any ambiguity about whether/when
this patch should be merged (probably not yet).

					-Alex

			=======================

 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 24 ++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
index 909039816a216..0e3bbdaf4661f 100644
--- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
+++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts
@@ -955,11 +955,35 @@ pcie@3,0 {
 			bus-range = <0x5 0xff>;
 
 			dev@0,0 {
+				compatible = "pci1179,0220";
 				reg = <0x50000 0x0 0x0 0x0 0x0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;	/* This will be updated dynamically */
+
+				pci-ep-bus@4 {
+					compatible = "simple-bus";
+					#address-cells = <1>;
+					#size-cells = <1>;
+					/* Map 0x0-0x1fffff to BAR 4 */
+					ranges = <0x0  0x4 0x0 0x0  0x200000>;
+				};
 			};
 
 			dev@0,1 {
+				compatible = "pci1179,0220";
 				reg = <0x50100 0x0 0x0 0x0 0x0>;
+				#address-cells = <3>;
+				#size-cells = <2>;
+				ranges;	/* This will be updated dynamically */
+
+				pci-ep-bus@4 {
+					compatible = "simple-bus";
+					#address-cells = <1>;
+					#size-cells = <1>;
+					/* Map 0x0-0x1fffff to BAR 4 */
+					ranges = <0x0  0x4 0x0 0x0  0x200000>;
+				};
 			};
 		};
 	};

base-commit: 705529dab1fa872d8b53b09c95e1b03a95573376
-- 
2.53.0