From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2973739A4CF for ; Sat, 3 Oct 2026 22:37:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.168.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791067058; cv=none; b=TAPtzsINp5I4GOVwRJFJ5JQkAYRCBR7/lpcTfq9Z94ZVpSxckm0ZAg7Uvslz7U03751selo9leIcU4bSQDd7bjwKTBj64p/fCMdqa5V6SbCJZlzzIMrTNDPPFNG96iQAH5zqvZjcMDOHXfoAhQln4yLR4M50SoMExU1zWSi45fQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1791067058; c=relaxed/simple; bh=hLkypq9fL/PGuQIzD987cxVCx0WleT2+L7/jCQBqQfA=; h=From:To:Cc:Subject:Date:Message-ID:MIME-Version; b=gsFaak1Q5VZdBOsSOTbWq9AIPQMUskE+NADyyYkJYQ8ojLunktY/X+j6WI3yzPyCX7BWUfuzg8/u4EWLK2KKWQ9yF5bWeOE4+EcSb+us3QHKKBeDINDAQ/Qe8XKtD8XkHixDAitJTH9am57RZkLK9roj2xFYKFeiJnvS4kBqIZE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=VSQoI0v5; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=PB3dOQlC; arc=none smtp.client-ip=205.220.168.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="VSQoI0v5"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="PB3dOQlC" Received: from pps.filterd (m0279867.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 693Koilp2257441 for ; Sat, 3 Oct 2026 22:37:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:message-id:mime-version :subject:to; s=qcppdkim1; bh=eAem2X14ObZm+rpDIaIE6FmNboclOYWffVU ntFzEfDk=; b=VSQoI0v5PDAVLttORLLqTpRNTnPcQWYNuFGM1/N3YLSOdVqLpbv DvpbQKXz0upZ1wpfmqClEuTEdqXwUOJ3G9keydaKuipG5CrAaUeoleqYBenKyYSM zC7NqlszxCJVC56gyjnX+/QioY27S+rUn27rBhSpPFYsPaco+n08LpGiJdrREhpP BvADdiZ/Blms/H3l+8Y6c1LrbA+SQ+AlGSf9TJqlHpb0g5gFEdOeEHK+S17C6wLK FZQaljNQYbuRcWN/U2iYALL/+ADy19ktHVGthv57fYgP25OhET6d6UVxzU+IFYbG E41UMpLiIzrU/TgL86oiu17YsqBOPjY9B1A== Received: from mail-pj1-f72.google.com (mail-pj1-f72.google.com [209.85.216.72]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4h2ssshwt5-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sat, 03 Oct 2026 22:37:35 +0000 (GMT) Received: by mail-pj1-f72.google.com with SMTP id 98e67ed59e1d1-39b77130a7fso650480a91.2 for ; Sat, 03 Oct 2026 15:37:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1791067054; x=1791671854; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to:content-type; bh=eAem2X14ObZm+rpDIaIE6FmNboclOYWffVUntFzEfDk=; b=PB3dOQlCxTu+aOXoa6WikRXT7WGbL2HUfWXrlu4AHPaGBBmbIUX5QWx63EGCtc6rED 2RNWMROCi2sPkyU3wDzXcxDlS4KbDaAhmjua7uwoeYUcyYZlk3NnqFwCINFOP0wOk0ki knmOYSRpWsBZkMZVK50sfwGBOVDcI33+hV8Qp+HbFhDzrV2gOHLFEbkONeNhrnQdYRou dcQLcOunJe6Lf55j88hfcil0jeuS84103Lk44gFaNVo3tby3DEqXDrSs5yExFzKRtlyZ thmQZCJJkqYSxXAxuNcEJ5n2lf0Zv09dl5P4aWu3wqJJ322z1940L8J+7/Cuk+ASlIFf jclg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1791067054; x=1791671854; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-gg:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=eAem2X14ObZm+rpDIaIE6FmNboclOYWffVUntFzEfDk=; b=GXIs76AhE1H0y8wO0VVj1kWUnhfBiE4jyY39I1PI4pR4e+gt22mnwTRWfq+5239mDs +wtjQZBVho/GRH0IWjPbZGclu0I9c/NXb7JuSAHyCpDjAo67G1VPuoUPljVwJwib8/mG RWROrt01utaTfb9OPZQsH9eaIkH5tkRzecgUtSOhQhqalqCjWQQviyvdxwd2fIKZ1K79 Fit5CcKmCwTWkqiLGT3sSbRzfqCR3DShM/5cGrDGF89f7Ut27oV0sQvbqCawsuWSIunu wf4FpFouXuCNKCJCtoWFGmmbqonZq6bOkINaGIN91ArnbtSZ+qGXGBHM2fSUWAFUd3DF cjog== X-Forwarded-Encrypted: i=1; AKwUvBxKpeI3HJ5OFI3OgaJFR1s989c303AislA5Un9DnmY4gHt3SdmLAgd7PWe2kf3qxsvOw9h7ddRiz8hHG1Q=@vger.kernel.org X-Gm-Message-State: AFq9FYJghZVtqEhweDAccZQaTs1Ik3pgwfJOfDUr1Qxv5WW+g5Z+GdDa XGAWpiwGhgn0FMHT/4sqwQ05W5Zp22hd+0LcEBEic+hgjqtFn12hinw3jqhxnbIGnZeEyalWBCf zTksEtfeq6P6Kc8n0soFfd+emHyXKQ2lxqCj9+uszdCw4Yv/h5LkBaUTxw3VXsudhec4= X-Gm-Gg: AYBFou3WfYuIq3T5x7dqNAMQzaVUFeg8iM3J8kF9pYTP9SQV/SM+z1NflM9wJbQoSAP QpY3dRetZ0xyd+HjRCttpaLB6BHnKL9kCOc8Gz9A4P9xxTWUb6GX3pMT6ZsivvNv3iZg9WQaV5H sZCX5S8AuFAZgT2PimamiVV+oIH9NFC0+a/SBvNDdGkLt6qSZV4QlcZ+iH/U7O1Sg6AlMq2os88 D+BMiZt/qGqMaw6ToWBQjZrrOpN7HKjqDoRmsej5QH4WgZyy/lVIr9AzvsVYBuAVptmvZIoQ0Nl kHWRBF2Qpb6l3BL0YnWGWcWQknSDeTW2FT6MMEjXEl1c8rgau4hIIVJPy/9bLqqKF92JiUyhgWB dhH+pDPWEaqZijQd9ZPgt+9StFAZ4LLuboRiyb86wQg369do= X-Received: by 2002:a17:90a:6097:b0:3a6:f1d2:57f8 with SMTP id 98e67ed59e1d1-3a6f1d269b3mr2445182a91.2.1791067054163; Sat, 03 Oct 2026 15:37:34 -0700 (PDT) X-Received: by 2002:a17:90a:6097:b0:3a6:f1d2:57f8 with SMTP id 98e67ed59e1d1-3a6f1d269b3mr2445174a91.2.1791067053583; Sat, 03 Oct 2026 15:37:33 -0700 (PDT) Received: from localhost (c-73-37-105-206.hsd1.or.comcast.net. [73.37.105.206]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a78e4664ebsm4499215a91.7.2026.10.03.15.37.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 03 Oct 2026 15:37:33 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Sean Paul , Konrad Dybcio , Akhil P Oommen , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH] drm/msm: Sync registers from mesa Date: Sat, 3 Oct 2026 15:37:22 -0700 Message-ID: <20261003223723.400020-1-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.55.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDAzMDA5MCBTYWx0ZWRfX+KLqat2yGVS3 yczHDCVqlNtOgmsrFeyjIt5l9sMO0DNRmfcuFHDo9LWzddM/HVAJTTCY5YddjsjWEtQzZH+dPEf U7fcS8J6mn1nYXnRRCm8/IHqQ3BwTP8= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDAzMDA5MCBTYWx0ZWRfX7d+7nlaRN/P0 9qffZq+kVQl4cAlAx9++gQjOaf+T+DhGv5T8a7nJoKZ8WFdg7EJ2dIVdHMPhM/Jsy1N9tNxnEIJ BQs2CG1NDHfS+NHr53JMyMUTPutUYrSpaZvSetNRcKSbyzt2D/E8clhd3cXziL11MNK4DKXGXem Y3p6wybm4OJ+RpZrJmeRkc10zH/qhdzAT0GwLvBSQhgAxU/OojxqxvI7A80D5O/JJ3iMdU3AV6Q z5oOOcde5QwE8hJ0cuyzZ4+pWIIGLKVx3SaWAkkjI1GHZaQm+Yk0FoCwx68Grr1rwU/n4t+dmHq 0+l3ohARVXp0C7p5AX0i/FbM8leeysBD/dbl+6Hc0e6aKo739aA4KfWOt6eGhRohtzWAKy3Flgt /IIvDb9z+e8V+G/JF4DHlTZZN1tPMIya704wzRD5bi/htLqfjYVSK3l5gRWv1DUkTEpyNlU7yut FLJW+4kVUCdCo794o9A== X-Proofpoint-GUID: p1hrCsmHnhxjZ6ptC6Se8tsCD31uZ8Sm X-Authority-Analysis: v=2.4 cv=HqjjiETS c=1 sm=1 tr=0 ts=6ac183af cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=19Wyn7e3V/0aNffMjNCMQw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=e5mUnYsNAAAA:8 a=EUspDBNiAAAA:8 a=0vnX1LisTAiW6trkSK4A:9 a=iS9zxrgQBfv6-_F4QbHw:22 a=Vxmtnl_E_bksehYqCbjh:22 X-Proofpoint-ORIG-GUID: p1hrCsmHnhxjZ6ptC6Se8tsCD31uZ8Sm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-03_04,2026-10-02_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 clxscore=1015 phishscore=0 bulkscore=0 adultscore=0 impostorscore=0 suspectscore=0 spamscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610030090 Sync changes from mesa commit 81fae85847d2 ("freedreno/registers: Sync xml changes back from kernel"). Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/registers/adreno/a2xx.xml | 25 +++--- drivers/gpu/drm/msm/registers/adreno/a5xx.xml | 17 ++++ drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 81 +++++++++++++------ .../drm/msm/registers/adreno/adreno_pm4.xml | 41 ++++++---- 5 files changed, 116 insertions(+), 50 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 081e79ea4652..c8381ac238ce 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -225,7 +225,7 @@ static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter, OUT_PKT7(ring, CP_REG_TO_MEM, 3); OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) | CP_REG_TO_MEM_0_CNT(2) | - CP_REG_TO_MEM_0_64B); + CP_REG_TO_MEM_0_IS_64B); OUT_RING(ring, lower_32_bits(iova)); OUT_RING(ring, upper_32_bits(iova)); } diff --git a/drivers/gpu/drm/msm/registers/adreno/a2xx.xml b/drivers/gpu/drm/msm/registers/adreno/a2xx.xml index 22caddaa0db9..66a9ad75131c 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a2xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a2xx.xml @@ -1228,10 +1228,15 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + + + + - - + + @@ -1527,12 +1532,12 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - - + + - + @@ -1544,7 +1549,7 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - + @@ -1796,10 +1801,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> - - - - + + + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml index 4af76b3750f7..e928ad4e518c 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a5xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a5xx.xml @@ -1804,6 +1804,9 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + + @@ -1832,6 +1835,13 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> + + The range GRAS_CL_CNTL.Z_CLAMP_ENABLE clamps to. Near and far, not + sorted as the a6xx equivalents are: a reversed depth range is written + reversed. + + + @@ -1976,6 +1986,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set + @@ -2058,6 +2069,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set + @@ -2070,6 +2082,7 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set + Z_READ_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER @@ -2114,6 +2127,8 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set + + Blits: @@ -2523,10 +2538,12 @@ bit 7 for RECTLIST (clear) when z32s8 (used for clear of depth32? not set + + diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml index e6e56969a9b8..cf2fb20203b7 100644 --- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml +++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml @@ -1388,7 +1388,7 @@ by a particular renderpass/blit. - + Has the size of data written to corresponding VSC_PRIM_STRM buffer. @@ -1396,7 +1396,7 @@ by a particular renderpass/blit. - + Has the size of data written to corresponding VSC pipe, ie. same thing that is written out to VSC_SIZE_BASE @@ -1461,8 +1461,10 @@ by a particular renderpass/blit. - - + + + + @@ -2170,12 +2172,12 @@ by a particular renderpass/blit. - + - - + + @@ -2561,10 +2563,8 @@ by a particular renderpass/blit. - - - + @@ -2761,7 +2761,22 @@ by a particular renderpass/blit. - + + + + + + + + + + + + + + + + @@ -2814,7 +2829,7 @@ by a particular renderpass/blit. - + @@ -2959,17 +2974,10 @@ by a particular renderpass/blit. - - + - - - - - - @@ -3288,7 +3296,29 @@ by a particular renderpass/blit. - + + + + + + + + + + + + @@ -3367,6 +3397,8 @@ by a particular renderpass/blit. + + @@ -3466,7 +3498,7 @@ by a particular renderpass/blit. - + @@ -4077,8 +4109,8 @@ by a particular renderpass/blit. - - + + @@ -4342,6 +4374,7 @@ by a particular renderpass/blit. + diff --git a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml index f185b541aa70..2723da19cf5b 100644 --- a/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml +++ b/drivers/gpu/drm/msm/registers/adreno/adreno_pm4.xml @@ -646,10 +646,10 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> Write to a scratch memory that is read by CP_REG_TEST with - SOURCE_SCRATCH_MEM set. It's not the same scratch as scratch registers. + SOURCE_OC_MEM set. It's not the same scratch as scratch registers. However it uses the same memory space. - + Executes an array of fixed-size command buffers where each @@ -1039,6 +1039,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) + + Draws (counter - NUM_VERTICES_OFFSET / 4) / STRIDE vertices, counter + read from NUM_VERTICES_BASE. a7xx divides the counter by four too, + earlier gens use it as-is. + @@ -1048,7 +1053,8 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + + @@ -1255,6 +1261,11 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) $dst = (($dst & $src0) rot $rotate) | $src1 Here "rot" means rotate left. + If SRCn_IS_REG, the corresponding src is a register offset, + otherwise it is an immediate. + + If DST_SCRATCH is set then the value modified is a scratch + ram address, instead of a register. @@ -1286,7 +1297,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) Treat things as 64B, allowing for a 64B atomic read of registers. --> - + @@ -1307,7 +1318,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + @@ -1327,7 +1338,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + @@ -1337,12 +1348,13 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) + + - - + @@ -1366,8 +1378,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - - + @@ -1954,13 +1965,13 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + written into by CP_MEM_TO_OC_MEM. --> + - + @@ -2277,10 +2288,10 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords) - + Best guess is that it is a faster way to fetch all the VSC_CHANNEL_VISIBILITY registers - and keep them in a local scratch memory instead of fetching every time + and keep them in a local on-chip memory instead of fetching every time when skipping IBs. -- 2.55.0