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From: Loic Poulain <loic.poulain@oss.qualcomm.com>
To: Robert Foss <rfoss@kernel.org>,
	Andi Shyti <andi.shyti@kernel.org>,
	Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	Loic Poulain <loic.poulain@oss.qualcomm.com>
Subject: [PATCH 0/5] i2c: qcom-cci: Runtime capability detection and improved read/write
Date: Sun, 04 Oct 2026 21:09:46 +0200	[thread overview]
Message-ID: <20261004-cci-imp-v1-0-227d12cb4829@oss.qualcomm.com> (raw)

Improves the Qualcomm CCI I2C driver in three related ways:

- Capabilities (queue sizes, max transfer lengths, supported I2C mode)
  are currently hardcoded per DT compatible string in a handful of
  cci_data instances. Patch 3 replaces the static per-compatible
  structs with a single version-sorted capability catalog resolved
  at runtime from CCI_HW_VERSION.

- The driver only supported single-command writes, capped at 11 bytes
  regardless of how much space the command queue actually has. Patches
  1 and 4 factor out the write-command queueing into a reusable helper
  and then add burst-write support, chunking longer writes
  across the whole queue instead of a single command's payload.

- The FIFO read path hardcoded a fixed 12-byte limit unrelated to the
  actual per-revision FIFO size, with a special-cased drain loop.
  Patch 5 simplify the FIFO read/drain-loop and derive the read-side
  limits from each revision's FIFO size

Also add overflow and underflow IRQ reporting, as queue limits are
now derived from the hardware capabilities and exercised more
aggressively.

Support for unbounded read and write transfers using the threshold
IRQ mechanism is planned as a follow-up. Such functionality is not
part of this series.

Depends on: https://lore.kernel.org/all/20260929-cci-clk-fix-v6-0-62a268cccb0f@oss.qualcomm.com/

Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
---
Loic Poulain (5):
      i2c: qcom-cci: Factor out write command queue programming
      i2c: qcom-cci: Handle and report queue overflow/underflow interrupts
      i2c: qcom-cci: Detect capabilities from CCI_HW_VERSION at runtime
      i2c: qcom-cci: Add burst write support
      i2c: qcom-cci: Extend i2c read limits based on CCI revision

 drivers/i2c/busses/i2c-qcom-cci.c | 286 ++++++++++++++++++++++++++------------
 1 file changed, 194 insertions(+), 92 deletions(-)
---
base-commit: eb271d18cdcee558095324dffaa53d9e6fe78882
change-id: 20260929-cci-imp-8ba384309942

Best regards,
-- 
Loic Poulain <loic.poulain@oss.qualcomm.com>


             reply	other threads:[~2026-10-04 19:09 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-04 19:09 Loic Poulain [this message]
2026-10-04 19:09 ` [PATCH 1/5] i2c: qcom-cci: Factor out write command queue programming Loic Poulain
2026-10-04 19:09 ` [PATCH 2/5] i2c: qcom-cci: Handle and report queue overflow/underflow interrupts Loic Poulain
2026-10-04 19:09 ` [PATCH 3/5] i2c: qcom-cci: Detect capabilities from CCI_HW_VERSION at runtime Loic Poulain
2026-10-04 19:09 ` [PATCH 4/5] i2c: qcom-cci: Add burst write support Loic Poulain
2026-10-04 19:09 ` [PATCH 5/5] i2c: qcom-cci: Extend i2c read limits based on CCI revision Loic Poulain

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