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There was no way to tell a NACK apart from a FIFO overflow/underflow in the logs. Decode the individual overflow/underflow bits for each queue and report them with dev_warn_ratelimited() as such errors are not expected in normal operation. While at it, change the HALT_ACK branches to OR into 'reset' instead of overwriting it, so a halt request for one master isn't dropped when the other master's HALT_ACK is handled in the same interrupt. Signed-off-by: Loic Poulain --- drivers/i2c/busses/i2c-qcom-cci.c | 38 ++++++++++++++++++++++++++++++++------ 1 file changed, 32 insertions(+), 6 deletions(-) diff --git a/drivers/i2c/busses/i2c-qcom-cci.c b/drivers/i2c/busses/i2c-qcom-cci.c index c4bb97868c54de636be756328ca7ee4e46e6b400..099da0069251681cc52e351fb656bd73e78a96c9 100644 --- a/drivers/i2c/busses/i2c-qcom-cci.c +++ b/drivers/i2c/busses/i2c-qcom-cci.c @@ -54,10 +54,18 @@ #define CCI_IRQ_STATUS_0 0xc0c #define CCI_IRQ_STATUS_0_I2C_M0_RD_DONE BIT(0) #define CCI_IRQ_STATUS_0_I2C_M0_Q0_REPORT BIT(4) +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_UNDERFLOW BIT(5) +#define CCI_IRQ_STATUS_0_I2C_M0_Q0_OVERFLOW BIT(6) #define CCI_IRQ_STATUS_0_I2C_M0_Q1_REPORT BIT(8) +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_UNDERFLOW BIT(9) +#define CCI_IRQ_STATUS_0_I2C_M0_Q1_OVERFLOW BIT(10) #define CCI_IRQ_STATUS_0_I2C_M1_RD_DONE BIT(12) #define CCI_IRQ_STATUS_0_I2C_M1_Q0_REPORT BIT(16) +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_UNDERFLOW BIT(17) +#define CCI_IRQ_STATUS_0_I2C_M1_Q0_OVERFLOW BIT(18) #define CCI_IRQ_STATUS_0_I2C_M1_Q1_REPORT BIT(20) +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_UNDERFLOW BIT(21) +#define CCI_IRQ_STATUS_0_I2C_M1_Q1_OVERFLOW BIT(22) #define CCI_IRQ_STATUS_0_RST_DONE_ACK BIT(24) #define CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK BIT(25) #define CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK BIT(26) @@ -177,12 +185,12 @@ static irqreturn_t cci_isr(int irq, void *dev) } if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_Q0Q1_HALT_ACK)) { - reset = CCI_RESET_CMD_M0_MASK; + reset |= CCI_RESET_CMD_M0_MASK; ret = IRQ_HANDLED; } if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_Q0Q1_HALT_ACK)) { - reset = CCI_RESET_CMD_M1_MASK; + reset |= CCI_RESET_CMD_M1_MASK; ret = IRQ_HANDLED; } @@ -190,22 +198,40 @@ static irqreturn_t cci_isr(int irq, void *dev) writel(reset, cci->base + CCI_RESET_CMD); if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M0_ERROR)) { + cci->master[0].status = -EIO; + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_NACK_ERR || val & CCI_IRQ_STATUS_0_I2C_M0_Q1_NACK_ERR) cci->master[0].status = -ENXIO; - else - cci->master[0].status = -EIO; + + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 0 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q0_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 0 underflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q1_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 1 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M0_Q1_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 0 queue 1 underflow\n"); writel(CCI_HALT_REQ_I2C_M0_Q0Q1, cci->base + CCI_HALT_REQ); ret = IRQ_HANDLED; } if (unlikely(val & CCI_IRQ_STATUS_0_I2C_M1_ERROR)) { + cci->master[1].status = -EIO; + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_NACK_ERR || val & CCI_IRQ_STATUS_0_I2C_M1_Q1_NACK_ERR) cci->master[1].status = -ENXIO; - else - cci->master[1].status = -EIO; + + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 0 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q0_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 0 underflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q1_OVERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 1 overflow\n"); + if (val & CCI_IRQ_STATUS_0_I2C_M1_Q1_UNDERFLOW) + dev_warn_ratelimited(cci->dev, "master 1 queue 1 underflow\n"); writel(CCI_HALT_REQ_I2C_M1_Q0Q1, cci->base + CCI_HALT_REQ); ret = IRQ_HANDLED; -- 2.34.1