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Sun, 04 Oct 2026 03:28:00 -0700 (PDT) Received: from DESKTOP-NM9EKIA ([125.134.240.130]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3a78e4262cfsm6192927a91.6.2026.10.04.03.27.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 04 Oct 2026 03:27:59 -0700 (PDT) From: Joonhoe Kim <26rote@gmail.com> To: Rob Clark , Dmitry Baryshkov Cc: Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jun Nie , Jonathan Marek , Pengyu Luo , Alexander Koskovich , Neil Armstrong , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: [PATCH] drm/msm/dpu: round up the compressed INTF width Date: Sun, 4 Oct 2026 19:27:58 +0900 Message-ID: <20261004102758.84436-1-26rote@gmail.com> X-Mailer: git-send-email 2.55.0.windows.5 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit For DSI with DSC, drm_mode_to_intf_timing_params() scales the INTF active width by bpp / (3 * bits_per_component) and rounds down. The DSI host computes the same width with DIV_ROUND_UP, both for the pixel clock (dsi_adjust_pclk_for_compression()) and for the active width it programs (dsi_timing_setup(), from bytes per line). When the division is not exact the INTF line is one pclk shorter than the DSI line, and the DSI FIFO overflows. Example: a bonded DSI video-mode panel, 952 pixels per link, DSC 8 bpp at 10 bpc: 952 * 8 / 30 = 253.87, so the INTF uses 253 and the DSI 254. Round up, as the DSI host does. Qualcomm's downstream SDE driver also rounds this width up, and Pengyu Luo needed the same rounding on the Legion Y700 gen 4 [1]. Tested on a Lenovo Legion Tab Y700 gen 5 (SM8850) with that panel, with a module parameter selecting the rounding: rounding down, DPMS off/on gives no vblank and 14000-17000 DSI FIFO error interrupts per second (dsi_err_worker: status=4); rounding up, the picture comes back and there are no errors. Only tested on this device. Link: https://lore.kernel.org/all/CAH2e8h6oinKxN1ndcvHCSc+=bFLXVVDZVAVF0cQHoiaMvEwhPQ@mail.gmail.com/ [1] Fixes: f9ce482d7dc0 ("drm/msm/dpu: fix video mode DSC for DSI") Assisted-by: LLM Signed-off-by: Joonhoe Kim <26rote@gmail.com> --- This does not touch the divisor discussed in the RGB101010 thread (bits_per_component * 3 vs 24, with and without widebus); that patch was dropped from the series pending that discussion [2]. This one only makes the rounding match the DSI host. The panel here uses widebus. [2] https://lore.kernel.org/all/20260321-dsi-rgb101010-support-v4-0-eb28ecebbfe8@pm.me/ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index ba810f26ea30..2ac517db50fc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -134,8 +134,8 @@ static void drm_mode_to_intf_timing_params( * TODO: replace drm_dsc_get_bpp_int with logic to handle * fractional part if there is fraction */ - timing->width = timing->width * drm_dsc_get_bpp_int(dsc) / - (dsc->bits_per_component * 3); + timing->width = DIV_ROUND_UP(timing->width * drm_dsc_get_bpp_int(dsc), + dsc->bits_per_component * 3); timing->xres = timing->width; timing->dce_bytes_per_line = msm_dsc_get_bytes_per_line(dsc); } -- 2.43.0